On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

Indirect interconnection networks for high performance routers/switches

Routers form the backbone of the Internet; their kernel, structure, andconfiguration (scheduler) of the backplane (or switching fabrics) dominate the routers’performance, scalability, reliability and cost. As higher performance is required with therapid development of the network applications, router’s architecture has also evolvedfrom the shared backplane to switched backplane, which mainly uses the indirectinterconnection networks.The indirect interconnection networks include crossbar, MIN (multistageinterconnection networks) and some other irregular topologies. At present, most oftoday’s routers and switches are implemented on single crossbar with symmetric bufferarchitecture. In the first part of this dissertation, we introduce novel asymmetric bufferarchitecture for the crossbar in which a new port and a local shared bus are added. Wethen evaluate its performance and simulate under different bus arbitration and buffermanagement algorithms. Our studies indicate that we can get great improvement for thethroughput and low drop rate. Thus we could save a lot of expensive link bandwidth anddecrease the probability of congestion for the network.Single crossbar complexity increases at O(N2) in terms of crosspoint number,which become unacceptable for scalability as the port number (N) increases. A delta classself-routing MIN with complexity of O(N×log2N) has been widely used in the ATMswitches. But the reduction of crosspoint number results in considerable internal blocking.A number of scalable methods have been proposed to solve this problem. One of themuses more stages with recirculation architecture to reroute the deflected packets, whichgreatly increase the latency. In the second part of this dissertation, we propose aninterleaved multistage switching fabrics architecture and assess its throughput with ananalytical model and simulations. We compare this novel scheme with some previousparallel architectures and show its benefits. From extensive simulations under differenttraffic patterns and fault models, our interleaved architecture achieves better performancethan its counterpart of single panel fabric. Our interleaved scheme achieves speedups(over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns,respectively at maximum load (p=1). Moreover, the interleaved fabrics show greattolerance against internal hardware failures

Design of a fast and resource-efficient fault management system in optical networks to suit real-time multimedia applications

Today\u27s telecommunications networks are relying more and more on optical fibers as their physical medium. Currently the Wavelength Division Multiplexing technology enables hundreds of wavelengths to be multiplexed on a single fiber. Using this technology capacity can be dramatically increased, even to the order of Terabits per second. While WDM technology has given a satisfactory answer to the ever-increasing demand for capacity, there is still a problem which needs to be handled efficiently: survivability. Our proposed fault restoration system optimized between restoration cost and speed. We extended the concept of Forward Equivalence Class (FEC) in Multi Protocol Label switching (MPLS) to our proposed fault restoration system. Speed was found to be in the order of 1 to 3 microseconds using predesigned protection, depending on the configuration of the system. Optimization was done between restoration speed and cost by introducing a priority field in the packet header

A formalism for describing and simulating systems with interacting components.

This thesis addresses the problem of descriptive complexity presented by systems involving a high number of interacting components. It investigates the evaluation measure of performability and its application to such systems. A new description and simulation language, ICE and it's application to performability modelling is presented. ICE (Interacting ComponEnts) is based upon an earlier description language which was first proposed for defining reliability problems. ICE is declarative in style and has a limited number of keywords. The ethos in the development of the language has been to provide an intuitive formalism with a powerful descriptive space. The full syntax of the language is presented with discussion as to its philosophy. The implementation of a discrete event simulator using an ICE interface is described, with use being made of examples to illustrate the functionality of the code and the semantics of the language. Random numbers are used to provide the required stochastic behaviour within the simulator. The behaviour of an industry standard generator within the simulator and different methods of number allocation are shown. A new generator is proposed that is a development of a fast hardware shift register generator and is demonstrated to possess good statistical properties and operational speed. For the purpose of providing a rigorous description of the language and clarification of its semantics, a computational model is developed using the formalism of extended coloured Petri nets. This model also gives an indication of the language's descriptive power relative to that of a recognised and well developed technique. Some recognised temporal and structural problems of system event modelling are identified. and ICE solutions given. The growing research area of ATM communication networks is introduced and a sophisticated top down model of an ATM switch presented. This model is simulated and interesting results are given. A generic ICE framework for performability modelling is developed and demonstrated. This is considered as a positive contribution to the general field of performability research

A multidisciplinary approach to the development of low-cost high-performance lightwave networks

Our research focuses on high-speed distributed systems. We anticipate that our results will allow the fabrication of low-cost networks employing multi-gigabit-per-second data links for space and military applications. The recent development of high-speed low-cost photonic components and new generations of microprocessors creates an opportunity to develop advanced large-scale distributed information systems. These systems currently involve hundreds of thousands of nodes and are made up of components and communications links that may fail during operation. In order to realize these systems, research is needed into technologies that foster adaptability and scaleability. Self-organizing mechanisms are needed to integrate a working fabric of large-scale distributed systems. The challenge is to fuse theory, technology, and development methodologies to construct a cost-effective, efficient, large-scale system

A high speed fault-tolerant multimedia network and connectionless gateway for ATM networks.

by Patrick Lam Sze Fan.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 163-[170]).Chapter 1 --- Introduction --- p.1Chapter 2 --- Fault-tolerant CUM LAUDE NET --- p.7Chapter 2.1 --- Overview of CUM LAUDE NET --- p.7Chapter 2.2 --- Network architecture of CUM LAUDE NET --- p.8Chapter 2.3 --- Design of Router-node --- p.10Chapter 2.3.1 --- Architecture of the Router-node --- p.10Chapter 2.3.2 --- Buffers Arrangement of the Router-node --- p.12Chapter 2.3.3 --- Buffer transmission policies --- p.13Chapter 2.4 --- Protocols of CUM LAUDE NET --- p.14Chapter 2.5 --- Frame Format of CUM LAUDE NET --- p.15Chapter 2.6 --- Fault-tolerant (FT) and Auto-healing (AH) algorithms --- p.16Chapter 2.6.1 --- Overview of the algorithms --- p.16Chapter 2.6.2 --- Network Failure Scenarios --- p.18Chapter 2.6.3 --- Design and Implementation of the Fault Tolerant Algorithm --- p.19Chapter 2.6.4 --- Design and Implementation of the Auto Healing Algorithm --- p.26Chapter 2.6.5 --- Network Management Signals and Restoration Times --- p.27Chapter 2.6.6 --- Comparison of fault-tolerance features of other networks with the CUM LAUDE NET --- p.31Chapter 2.7 --- Chapter Summary --- p.31Chapter 3 --- Overview of the Asynchronous Transfer Mode (ATM) --- p.33Chapter 3.1 --- Introduction --- p.33Chapter 3.2 --- ATM Network Interfaces --- p.34Chapter 3.3 --- ATM Virtual Connections --- p.35Chapter 3.4 --- ATM Cell Format --- p.36Chapter 3.5 --- ATM Address Formats --- p.36Chapter 3.6 --- ATM Protocol Reference Model --- p.38Chapter 3.6.1 --- The ATM Layer --- p.39Chapter 3.6.2 --- The ATM Adaptation Layer --- p.39Chapter 3.7 --- ATM Signalling --- p.44Chapter 3.7.1 --- ATM Signalling Messages and Call Setup Procedures --- p.45Chapter 3.8 --- Interim Local Management Interface (ILMI) --- p.47Chapter 4 --- Issues of Connectionless Gateway --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- The Issues --- p.50Chapter 4.3 --- ATM Internetworking --- p.51Chapter 4.3.1 --- LAN Emulation --- p.52Chapter 4.3.2 --- IP over ATM --- p.53Chapter 4.3.3 --- Comparing IP over ATM and LAN Emulation --- p.59Chapter 4.4 --- Connection Management --- p.61Chapter 4.4.1 --- The Indirect Approach --- p.62Chapter 4.4.2 --- The Direct Approach --- p.63Chapter 4.4.3 --- Comparing the two approaches --- p.64Chapter 4.5 --- Protocol Conversion --- p.65Chapter 4.5.1 --- Selection of Protocol Converter --- p.68Chapter 4.6 --- Packet Forwarding Modes --- p.68Chapter 4.7 --- Bandwidth Assignment --- p.70Chapter 4.7.1 --- Bandwidth Reservation --- p.71Chapter 4.7.2 --- Fast Bandwidth Reservation --- p.72Chapter 4.7.3 --- Bandwidth Advertising --- p.72Chapter 4.7.4 --- Bandwidth Advertising with Cell Drop Detection --- p.73Chapter 4.7.5 --- Bandwidth Allocation on Source Demand --- p.73Chapter 4.7.6 --- The Common Problems --- p.74Chapter 5 --- Design and Implementation of the Connectionless Gateway --- p.77Chapter 5.1 --- Introduction --- p.77Chapter 5.1.1 --- Functions Definition of Connectionless Gateway --- p.79Chapter 5.2 --- Hardware Architecture of the Connectionless Gateway --- p.79Chapter 5.2.1 --- Imposed Limitations --- p.82Chapter 5.3 --- Software Architecture of the Connectionless Gateway --- p.83Chapter 5.3.1 --- TCP/IP Internals --- p.84Chapter 5.3.2 --- ATM on Linux --- p.85Chapter 5.4 --- Network Architecture --- p.88Chapter 5.4.1 --- IP Addresses Assignment --- p.90Chapter 5.5 --- Internal Structure of Connectionless Gateway --- p.90Chapter 5.5.1 --- Protocol Stacks of the Gateway --- p.90Chapter 5.5.2 --- Gateway Operation by Example --- p.93Chapter 5.5.3 --- Routing Table Maintenance --- p.97Chapter 5.6 --- Additional Features --- p.105Chapter 5.6.1 --- Priority Output Queues System --- p.105Chapter 5.6.2 --- Gateway Performance Monitor --- p.112Chapter 5.7 --- Setup an Operational ATM LAN --- p.117Chapter 5.7.1 --- SVC Connections --- p.117Chapter 5.7.2 --- PVC Connections --- p.119Chapter 5.8 --- Application of the Connectionless Gateway --- p.120Chapter 6 --- Performance Measurement of the Connectionless Gateway --- p.121Chapter 6.1 --- Introduction --- p.121Chapter 6.2 --- Experimental Setup --- p.121Chapter 6.3 --- Measurement Tools of the Experiments --- p.123Chapter 6.4 --- Descriptions of the Experiments --- p.124Chapter 6.4.1 --- Log Files --- p.125Chapter 6.5 --- UDP Control Rate Test --- p.126Chapter 6.5.1 --- Results and analysis of the UDP Control Rate Test --- p.127Chapter 6.6 --- UDP Maximum Rate Test --- p.138Chapter 6.6.1 --- Results and analysis of the UDP Maximum Rate Test --- p.138Chapter 6.7 --- TCP Maximum Rate Test --- p.140Chapter 6.7.1 --- Results and analysis of the TCP Maximum Rate Test --- p.140Chapter 6.8 --- Request/Response Test --- p.144Chapter 6.8.1 --- Results and analysis of the Request/Response Test --- p.144Chapter 6.9 --- Priority Queue System Verification Test --- p.149Chapter 6.9.1 --- Results and analysis of the Priority Queue System Verifi- cation Test --- p.150Chapter 6.10 --- Other Observations --- p.153Chapter 6.11 --- Solutions to Improve the Performance --- p.154Chapter 6.12 --- Future Development --- p.157Chapter 7 --- Conclusion --- p.158Bibliography --- p.163A List of Publications --- p.17

Performance evaluation of Fast Ethernet, ATM and Myrinet under PVM

Congestion in network switches can limit the communication traffic between Parallel Virtual Machine (PVM) nodes in a parallel computation. The research introduces a new benchmark to evaluate the performance of PVM in various networking environments. The benchmark is used to achieve a better understanding of performance limitations in parallel computing that are imposed by the choice of the network. The networks considered here are Fast Ethernet, Asynchronous Transfer Mode (ATM) OC-3c (155Mb/s) and Myrinet. Together, they represent an interesting range of alternatives for parallel cluster computing. A characterization of network delays and throughput and a comparison of the expected costs of the three environments are developed to provide a basis for an informed decision on the networking methods and topology for a parallel database that is being considered for FBI\u27s National DNA Indexing System (NDIS)[17]. This network is used for communications among the nodes of the parallel machine; thus the security requirements defined for the FBI\u27s Criminal Justice Information Services Division Wide Area Network (CJIS-WAN) [12] are not a concern

A Performance evaluation of several ATM switching architectures

The goal of this thesis is to evaluate the performance of three Asynchronous Transfer Mode switching architectures. After examining many different ATM switching architectures in literature, the three architectures chosen for study were the Knockout switch, the Sunshine switch, and the Helical switch. A discrete-time, event driven system simulator, named ProModel, was used to model the switching behavior of these architectures. Each switching architecture was modeled and studied under at least two design configurations. The performance of the three architectures was then investigated under three different traffic types representative of traffic found in B-ISDN: random, constant bit rate, and bursty. Several key performance parameters were measured and compared between the architectures. This thesis also explored the implementation complexities and fault tolerance of the three selected architectures