3 research outputs found
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Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios
Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver.
In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF.
A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception
Reconfigurable architectures for the next generation of mobile device telecommunications systems
Mobile devices have become a dominant tool in our daily lives. Business and
personal usage has escalated tremendously since the emergence of smartphones
and tablets. The combination of powerful processing in mobile devices, such as
smartphones and the Internet, have established a new era for communications
systems. This has put further pressure on the performance and efficiency of
telecommunications systems in delivering the aspirations of users. Mobile device
users no longer want devices that merely perform phone calls and messaging.
Rather, they look for further interactive applications such as video streaming,
navigation and real time social interaction. Such applications require a new set of
hardware and standards. The WiFi (IEEE 802.11) standard has been at the forefront
of reliable and high-speed internet access telecommunications. This is due to its
high signal quality (quality of service) and speed (throughput). However, its limited
availability and short range highlights the need for further protocols, in particular
when far away from access points or base stations. This led to the emergence of 3G
followed by 4G and the upcoming 5G standard that, if fully realised, will provide
another dimension in “anywhere, anytime internet connectivity.” On the other
hand, the WiMAX (IEEE 802.16) standard promises to exceed the WiFi signal
coverage range. The coverage range could be extended to kilometres at least with a
better or similar WiFi signal level.
This thesis considers a dynamically reconfigurable architecture that is capable of
processing various modules within telecommunications systems. Forward error
correction, coder and navigation modules are deployed in a unified low power
communication platform. These modules have been selected since they are among
those with the highest demand in terms of processing power, strict processing time
or throughput. The modules are mainly realised within WiFi and WiMAX systems
in addition to global positioning systems (GPS). The idea behind the selection of
these modules is to investigate the possibility of designing an architecture capable
of processing various systems and dynamically reconfiguring between them. The
GPS system is a power-hungry application and, at the same time, it is not needed
all of the time. Hence, one key idea presented in this thesis is to effectively exploit
the dynamic reconfiguration capability so as to reconfigure the architecture (GPS)
when it is not needed in order to process another needed application or function
such as WiFi or WiMAX. This will allow lower energy consumption and the
optimum usage of the hardware available on the device.
This work investigates the major current coarse-grain reconfigurable architectures.
A novel multi-rate convolution encoder is then designed and realised as a
reconfigurable fabric. This demonstrates the ability to adapt the algorithms
involved to meet various requirements. A throughput of between 200 and 800
Mbps has been achieved for the rates 1/2 to 7/8, which is a great achievement for
the proposed novel architecture. A reconfigurable interleaver is designed as a
standalone fabric and on a dynamically reconfigurable processor. High throughputs
exceeding 90 Mbps are achieved for the various supported block sizes. The Reed
Solomon coder is the next challenging system to be designed into a dynamically
reconfigurable processor. A novel Galois Field multiplier is designed and
integrated into the developed Reed Solomon reconfigurable processor. As a result
of this work, throughputs of 200Mbps and 93Mbps respectively for RS encoding
and decoding are achieved. A GPS correlation module is also investigated in this
work. This is the main part of the GPS receiver responsible for continuously
tracking GPS satellites and extracting messages from them. The challenging aspect
of this part is its real-time nature and the associated critical time constraints. This
work resulted in a novel dynamically reconfigurable multi-channel GPS correlator
with up to 72 simultaneous channels.
This work is a contribution towards a global unified processing platform that is
capable of processing communication-related operations efficiently and
dynamically with minimum energy consumption
Intelligent Circuits and Systems
ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society. This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering