Modes of Random Lasers

In conventional lasers, the optical cavity that confines the photons also determines essential characteristics of the lasing modes such as wavelength, emission pattern, ... In random lasers, which do not have mirrors or a well-defined cavity, light is confined within the gain medium by means of multiple scattering. The sharp peaks in the emission spectra of semiconductor powders, first observed in 1999, has therefore lead to an intense debate about the nature of the lasing modes in these so-called lasers with resonant feedback. In this paper, we review numerical and theoretical studies aimed at clarifying the nature of the lasing modes in disordered scattering systems with gain. We will discuss in particular the link between random laser modes near threshold (TLM) and the resonances or quasi-bound (QB) states of the passive system without gain. For random lasers in the localized regime, QB states and threshold lasing modes were found to be nearly identical within the scattering medium. These studies were later extended to the case of more lossy systems such as random systems in the diffusive regime where differences between quasi-bound states and lasing modes were measured. Very recently, a theory able to treat lasers with arbitrarily complex and open cavities such as random lasers established that the TLM are better described in terms of the so-called constant-flux states.Comment: Review paper submitted to Advances in Optics and Photonic

Accelerating host-compiled simulation by modifying IR code: industrial application in the spatial domain

Space applications rely on long and complex design processes, as they must deal with strict non-functional requirements such as criticality, timeliness, reliability and safety. The huge number of analysis and evaluations performed requires powerful simulations technologies combining high simulation speed and accuracy. Host-compiled simulation is a powerful approach to achieve fast, timed simulation of software running in complex embedded systems. However, in the general term, there is still the need of improving the speed and accuracy of these solutions, and there is a lack of host-compiled approaches oriented to space applications. To solve the first point, this paper presents an alternative that modifies the standard solution of adding the modeling of the cross-compiled control flow in the host computer by modifying the compiler's intermediate representation. That way, the host binary naturally follows the cross-compiled binary flow, avoiding a separate modeling, and improving simulation speed while maintaining accuracy. Additionally, the paper focuses on LEON processor, commonly used by the European Space Agency (ESA).This work has been funded by FEDER/Ministerio de Ciencia, Innovación y Universidades - Agencia Estatal de Investigación/ TEC2017-86722-C4-3-R and the EC through the FP7-JTI 621429 EMC2 project

A mixed-level virtual prototyping environment for refinement-based design environment

The Communication Architecture Template Tree (CATtree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixedlevel simulation environment that is useful for the functional verification of partially refined system models. We employed SystemC, GNU Gdb and a HDL simulator for the simulation of CATtree-based TLM, SW and HW, respectively. We also employed a new operating system, DEOS so that each SystemC-based TLMs can be cross-compiled to be executed as software models on the target processors. We evaluated the flexibility and simulation performance of the virtual simulation environment with an H.264 decoder design example

An Explorative Study of Kentucky Teacher Leader Graduate Programs: Response to Policy Change

Teacher leadership is a growing practice for supporting K-12 teachers and students. Recent policy regulations in the Commonwealth of Kentucky mandated a change in the professional standards used by approved graduate programs that prepare teacher leaders. To support this foundational change, program leaders designed programmatic goals, curriculum, structure, and tasks to align with the Teacher Leader Model Standards that emphasize promising research-based practices. The programs support development of teacher leadership through pedagogical approach, requirements, and programmatic structure. Using a qualitative, multi-site case-study approach, this dissertation explored Kentucky teacher leadership graduate programs to understand how teacher leaders were formally prepared. Program leaders, faculty, and review of materials communicated how their programs support teacher leaders within and beyond the classroom, thus serving the greater community. Professional learning for teachers as leaders was a focus of this study. The study sought to uncover how formal development occurs within the context of Education Professional Standards Board (EPSB)-approved graduate leadership programs. Layered Framework for, Models of, and Development within Teacher Leadership served as the dissertation’s conceptual framework. Because the new legislative shift to Teacher Leader Model Standards was effective August 1, 2019, conclusions drawn from this study added to the literature base and field of study. This case study provided a foundational exploration of how high-graduate yielding teacher leader programs (TLPs) in Kentucky institutions formally prepared teacher leaders leading up to, during, and after new legislation adoption. The TLPs of interest are those approved by EPSB. In addition to programmatic individuals’ dialogue, a Teacher Leader Review Committee member shared the process and intention behind the adoption of the Teacher Leader Model Standards for Kentucky’s EPSB-approved teacher leadership programs

Examining Teacher Leadership: The Perceived Challenges of Being a Teacher Leader

Today’s school leaders recognize that one person, mainly the principal, cannot adequately address the needs of all members of the school community. Many principals rely on teacher leaders to lead alongside them to further school improvement, knowing that the traditional way of thinking of school leadership as being the sole role of the principal is no longer effective or efficient. While K-12 teachers typically have a strong background in child development, psychology, and pedagogy, many lack experience in leading and facilitating adults and have little background in adult learning theory. The purpose of this research is to determine how K-12 teacher leaders perceive the challenges of leading and facilitating adults. Working within Knowles Andragogy Adult Learning Theory, this phenomenological qualitative study will analyze five to eight teacher leaders in rural, North Dakota school districts. Data will be collected through open-ended interview questions and be analyzed through coding the transcriptions of the interviews. My goal is that this study can be utilized to inform further research in the area of teacher leader development for both school districts and higher education institutions

Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators

Spiking Neural Networks (SNNs) offer a promising alternative to Artificial Neural Networks (ANNs) for deep learning applications, particularly in resource-constrained systems. This is largely due to their inherent sparsity, influenced by factors such as the input dataset, the length of the spike train, and the network topology. While a few prior works have demonstrated the advantages of incorporating sparsity into the hardware design, especially in terms of reducing energy consumption, the impact on hardware resources has not yet been explored. This is where design space exploration (DSE) becomes crucial, as it allows for the optimization of hardware performance by tailoring both the hardware and model parameters to suit specific application needs. However, DSE can be extremely challenging given the potentially large design space and the interplay of hardware architecture design choices and application-specific model parameters. In this paper, we propose a flexible hardware design that leverages the sparsity of SNNs to identify highly efficient, application-specific accelerator designs. We develop a high-level, cycle-accurate simulation framework for this hardware and demonstrate the framework's benefits in enabling detailed and fine-grained exploration of SNN design choices, such as the layer-wise logical-to-hardware ratio (LHR). Our experimental results show that our design can (i) achieve up to $76\%$ reduction in hardware resources and (ii) deliver a speed increase of up to $31.25\times$, while requiring $27\%$ fewer hardware resources compared to sparsity-oblivious designs. We further showcase the robustness of our framework by varying spike train lengths with different neuron population sizes to find the optimal trade-off points between accuracy and hardware latency

Early and Accurate Modeling of Streaming Embedded Applications

This thesis presents automatic generation of fast and accurate timed models of streaming embedded applications, before the complete software-hardware platform is available. We focus on streaming applications, because they tend to be the most compute-intensive applications on mobile devices. Therefore, it is critical to optimize the hardware-software platform for streaming applications, as early as possible in the design process. As such, fast, accurate and early models are essential for hardware-software optimization. Our design methodology is as follows. First, a measurement model is generated and executed, on the target processor, to predict the computation delays in an application. Next, the delays are annotated in the application code to generate a host-compiled model of the application. Our experiments show that such models can be generated and simulated at very high speed and accurately predict the computation load offered by the application. Our results with large streaming media applications, such as music and voice codecs, show that the estimation errors are less than 3.3%, while providing very high simulation speed. Therefore, using our models, embedded system designers can perform early optimizations to the system architecture with high confidence