Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump (design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc.) that are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were find based on the construct of the time response characteristics of the pump sub-block and finding of the maximal voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc. Synthesis process includes the design of the pump functional blocks with dominant real properties, which are described based on BSIM equations for long channel MOSFET. The pump stage complex model is applicated for estimation of the number of pump stages via state-space model description and using of the interpolation polynomial functions in the algorithm. It involves the construction of the time response characteristic due to the state variables and prediction of the number of the pump stages for the next cycle based on the previous data. Optimization of the pump area is based on the minimizing of the main capacitor in each of the pump stages (number of the pump stages must be increased to obtain the desired output voltage value.) Access is designed to stress the maximum pump voltage efficiency. The whole procedure is summarized in the practical example, in which the solution is shown both in terms of maximal voltage efficiency and the optimal pump area on a chip with respect to the clock signal frequency. Added functions of the design environment are explained, inclusive of the designed pump netlist generating for professional design environment Mentor Graphics including the real models of components that are available in library MGC Design Kit. The procedure gives designer credible results without long timeconsuming optimization process. In addition, the complex model allows the inclusion effects of higher-levels

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Equalization-Based Digital Background Calibration Technique for Pipelined ADCs

In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC

MODELING AND CONTROL OF DIRECT-CONVERSION HYBRID SWITCHED-CAPACITOR DC-DC CONVERTERS

Efficient power delivery is increasingly important in modern computing, communications, consumer and other electronic systems, due to the high power demand and thermal concerns accompanied by performance advancements and tight packaging. In pursuit of high efficiency, small physical volume, and flexible regulation, hybrid switched-capacitor topologies have emerged as promising candidates for such applications. By incorporating both capacitors and inductors as energy storage elements, hybrid topologies achieve high power density while still maintaining soft charging and efficient regulation characteristics. However, challenges exist in the hybrid approach. In terms of reliability, each flying capacitor should be maintained at a nominal `balanced\u27 voltage for robust operation (especially during transients and startup), complicating the control system design. In terms of implementation, switching devices in hybrid converters often need complex gate driving circuits which add cost, area, and power consumption. This dissertation explores techniques that help to mitigate the aforementioned challenges. A discrete-time state space model is derived by treating the hybrid converter as two subsystems, the switched-capacitor stage and the output filter stage. This model is then used to design an estimator that extracts all flying capacitor voltages from the measurement of a single node. The controllability and observability of the switched-capacitor stage reveal the fundamental cause of imbalance at certain conversion ratios. A new switching sequence, the modified phase-shifted pulse width modulation, is developed to enable natural balance in originally imbalanced scenarios. Based on the model, a novel control algorithm, constant switch stress control, is proposed to achieve both output voltage regulation and active balance with fast dynamics. Finally, the design technique and test result of an integrated hybrid switched-capacitor converter are reported. A proposed gate driving strategy eliminates the need for external driving supplies and reduces the bootstrap capacitor area. On-chip mixed signal control ensures fast balancing dynamics and makes hard startup tolerable. This prototype achieves 96.9\% peak efficiency at 5V:1.2V conversion and a startup time of 12$\mu s$, which is over 100 times faster than the closest prior art. With the modeling, control, and design techniques introduced in this dissertation, the application of hybrid switched-capacitor converters may be extended to scenarios that were previously challenging for them, allowing enhanced performance compared to using traditional topologies. For problems that may require future attention, this dissertation also points to possible directions for further improvements

Linearized large signal modeling, analysis, and control design of phase-controlled series-parallel resonant converters using state feedback

This paper proposes a linearized large signal state-space model for the fixed-frequency phase-controlled series-parallel resonant converter. The proposed model utilizes state feedback of the output filter inductor current to perform linearization. The model combines multiple-frequency and average state-space modeling techniques to generate an aggregate model with dc state variables that are relatively easier to control and slower than the fast resonant tank dynamics. The main objective of the linearized model is to provide a linear representation of the converter behavior under large signal variation which is suitable for faster simulation and large signal estimation/calculation of the converter state variables. The model also provides insight into converter dynamics as well as a simplified reduced order transfer function for PI closed-loop design. Experimental and simulation results from a detailed switched converter model are compared with the proposed state-space model output to verify its accuracy and robustness

Methodology for characterizing electric power system response and locating the energized capacitor banks using conventional power quality data

textA relatively small harmonic current with frequencies near or at the power system parallel resonant frequencies could excite the power system into a resonance condition. While a capacitor bank is not the root cause of the condition, it facilitates and helps cause the problem. This is because when the capacitor bank is energized, the system resonant frequency could shift closer to existing harmonic frequencies produced by nonlinear loads. Therefore, the objective of this dissertation is to quantify the power system characteristics corresponding to the parallel resonant frequencies and system damping. Additionally, since a capacitor bank actively facilitates the resonance condition, the relative or exact location of the involved bank must be determined. This dissertation first presents a practical and accurate methodology to estimate system parallel resonant frequencies by performing spectral analysis of the voltage and current transient data immediately after the capacitor bank switching. The proposed method is also robust in that the accuracy of the resulting estimates is not affected by prevalent harmonics in the system. This dissertation provides two efficient algorithms for estimating the system damping parameters using the Hilbert and analytic wavelet transforms. These algorithms take advantage of the principle of an asymptotic or weaklymodulated signal, for which the signal phase varies much more rapidly than the amplitude. The zero-input voltage response or free response of the capacitor bank energizing can be categorized into these asymptotic signals, and one can assign a unique time-varying amplitude with the system damping information and phase pair by building analytic signals. System model reduction theory also allows us to interpret or quantify this damping as an effective X/R ratio. This dissertation defines two fundamental signatures of shunt capacitor bank energizing. It demonstrates that these two signatures can be utilized to accurately determine the relative location of an energized capacitor bank whether it is upstream or downstream from the monitoring location. This dissertation also presents an efficient and accurate methodology for finding the exact location of an energized capacitor bank. Once a PQ monitor is found to be upstream from the capacitor bank by the relative location finding algorithm, the proposed algorithm can further determine the exact location of the switched capacitor bank by estimating the distance between the PQ monitor and the energized capacitor bank. Thus, one can pinpoint the energized capacitor bank causing the resonance.Electrical and Computer Engineerin