Adaptive Routing Approaches for Networked Many-Core Systems

Through advances in technology, System-on-Chip design is moving towards integrating tens to hundreds of intellectual property blocks into a single chip. In such a many-core system, on-chip communication becomes a performance bottleneck for high performance designs. Network-on-Chip (NoC) has emerged as a viable solution for the communication challenges in highly complex chips. The NoC architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth. Furthermore, the combined benefits of 3D IC and NoC schemes provide the possibility of designing a high performance system in a limited chip area. The major advantages of 3D NoCs are the considerable reductions in average latency and power consumption. There are several factors degrading the performance of NoCs. In this thesis, we investigate three main performance-limiting factors: network congestion, faults, and the lack of efficient multicast support. We address these issues by the means of routing algorithms. Congestion of data packets may lead to increased network latency and power consumption. Thus, we propose three different approaches for alleviating such congestion in the network. The first approach is based on measuring the congestion information in different regions of the network, distributing the information over the network, and utilizing this information when making a routing decision. The second approach employs a learning method to dynamically find the less congested routes according to the underlying traffic. The third approach is based on a fuzzy-logic technique to perform better routing decisions when traffic information of different routes is available. Faults affect performance significantly, as then packets should take longer paths in order to be routed around the faults, which in turn increases congestion around the faulty regions. We propose four methods to tolerate faults at the link and switch level by using only the shortest paths as long as such path exists. The unique characteristic among these methods is the toleration of faults while also maintaining the performance of NoCs. To the best of our knowledge, these algorithms are the first approaches to bypassing faults prior to reaching them while avoiding unnecessary misrouting of packets. Current implementations of multicast communication result in a significant performance loss for unicast traffic. This is due to the fact that the routing rules of multicast packets limit the adaptivity of unicast packets. We present an approach in which both unicast and multicast packets can be efficiently routed within the network. While suggesting a more efficient multicast support, the proposed approach does not affect the performance of unicast routing at all. In addition, in order to reduce the overall path length of multicast packets, we present several partitioning methods along with their analytical models for latency measurement. This approach is discussed in the context of 3D mesh networks.Siirretty Doriast

Traffic Prediction for NoCs using Fuzzy Logic

Proceedings DOI: 10.5445/KSP/1000021732 (https://doi.org/10.5445/KSP/1000021732)Networks on Chip provide faster communication and higher throughput for chip multiprocessor systems than conventional bus systems. Having multiple processing elements on one chip, however, leads to a large number of message transfers in the NoC. The consequence is that more blocking occurs and time and power is wasted with waiting until the congestion is dissolved. With knowledge of future communication patterns, blocking could be avoided. Therefore, in this paper a model is introduced to predict future communication patterns to avoid network congestion. Our model uses a fuzzy based algorithm to predict end-to-end communication. The presented model accurately predictions for up to 10 time intervals for continuous patterns. Communication patterns with non-continuous behaviors, such as fast changes from peak to zero, can also be predicted accurately for the next 1 to 2 time intervals to come. The model is a first step to predict future communication patterns. In addition, some limitations are identified that must be solved in order to improve the model

Fuzzy-based fault-tolerant and instant synchronization routing technique in wireless sensor network for rapid transit system

In the present era, rapid transits are one of the most affordable means of public transport with various useful integrated application systems. The majority of the integrated applications are deployed in concern over safety and precautionary measures against the worst side-effects of unfortunate emergencies. For such cases, high-end reliable and autonomous systems provide possible positive solutions. Wireless Sensor Network is one of the suitable choices for rapid transit applications to gain positive results with inexpensive implementation cost. However, managing few network consequences like fault tolerance, energy balancing and routing critical informative packets are considered to be the challenging task due to their limited resource usage restriction. In this paper, a novel fuzzy logic-based fault tolerance and instant synchronized routing technique have been proposed specifically for the rapid transit system. On utilizing the fuzzy logic concepts, most of the computational complexities and uncertainties of the system is reduced. The central thematic of the proposed design is concerned over the synchronized routing and permanent faults which abruptly depicts the non-functional nature of the sensor nodes during normal operations. Moreover, our proposed simulation outcomes proved to be improvised evidence on obtaining maximum packet delivery ratio which tends to handle an emergency situation in the compartments of rapid transits

A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors

Recent developments in reconfigurable multiprocessor system on chip (MPSoC) have offered system designers a great amount of flexibility to exploit task concurrency with higher throughput and less energy consumption. This paper presents a novel fuzzy logic reconfiguration engine (FLRE) for coarse grain MPSoC reconfiguration that facilitates to identify an optimum balance between power and performance of the system. The FLRE is composed on two levels of abstraction layers. The system selects an optimal configuration of Level 1 / Level 2 cache size and Associativity, processor operating frequency and voltage, the number of cores based on miss rate, and energy and throughput information of the system both at core and SoC level. An 8-core symmetric chip multiprocessor has been used to evaluate the proposed scheme. The results show an overall decrease of energy consumption with not more than 30% decrease in the throughput

A Machine Learning-Based Intelligence Approach for Multiple-Input/Multiple-Output Routing in Wireless Sensor Networks

Computational intelligence methods play an important role for supporting smart networks operations, optimization, and management. In wireless sensor networks (WSNs), increasing the number of nodes has a need for transferring large volume of data to remote nodes without any loss. These large amounts of data transmission might lead to exceeding the capacity of WSNs, which results in congestion, latency, and packet loss. Congestion in WSNs not only results in information loss but also burns a significant amount of energy. To tackle this issue, a practical computational intelligence approach for optimizing data transmission while decreasing latency is necessary. In this article, a Softmax-Regressed-Tanimoto-Reweight-Boost-Classification- (SRTRBC-) based machine learning technique is proposed for effective routing in WSNs. It can route packets around busy locations by selecting nodes with higher energy and lower load. The proposed SRTRBC technique is composed of two steps: route path construction and congestion-aware MIMO routing. Prior to constructing the route path, the residual energy of the node is determined. After that, the residual energy level is analyzed using softmax regression to determine whether or not the node is energy efficient. The energy-efficient nodes are located, and numerous paths between the source and sink nodes are established using route request and route reply. Following that, the SRTRBC technique is used for congestion-aware routing based on buffer space and bandwidth capability. The path that requires the least buffer space and has the highest bandwidth capacity is picked as the optimal route path among multiple paths. Finally, congestion-aware data transmission is used to minimize latency and data loss along the route path. The simulation considers a variety of performance metrics, including energy consumption, data delivery rate, data loss rate, throughput, and delay, in relation to the amount of data packets and sensor nodes.publishedVersio

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast