A study of Radiation-Tolerant Voltage-Controlled Oscillators designs in 65 nm bulk and 28 nm FDSOI CMOS technologies

Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices and communications systems that operate in radiation environments, where significant perturbations, especially in terms of phase noise, can be generated due to radiation particles. Among all the blocks that form a PLL system, previous research suggests the voltage-controlled oscillator (VCO) is one of the most critical components in terms of radiation tolerance and electric performance. Ring oscillators (ROs) and LC-tank VCOs have been commonly employed in high-performance PLLs. Nevertheless, both structures have drawbacks including a limited tuning range, high sensitivity to phase noise, limited radiation tolerance, and large design areas. In order to fulfill these high-performance requirements, a current-model logic (CML) based RO-VCO is presented as a possible solution capable of reducing the limitations of the commonly used structures and exploiting their advantages. The proposed hybrid VCO model includes passive components in its design which are the key parameters that define oscillation frequency of this structure. This tunable oscillator has been designed and tested in 65nm Bulk and 28 nm Fully depleted silicon-on-insulator (FDSOI) CMOS technologies The 65nm testchip was designed to compare the behavior of the proposed CML VCO with a current-starved RO and a radiation hardened by design (RHBD) LC-tank VCO in terms of tuning range, phase noise, Single event effect (SEE) sensitivity and design area. Simulations were carried out by applying a double exponential current pulse into different sensitive nodes of the three VCOs. In addition, SEE tests were conducted using pulsed laser experiments. Simulation and test results show that a CML VCO can effectively overcome the limitations presented by a RO-VCO and LC-tank VCO, achieving a wide range of tuning, and low sensitivity to noise and SEEs without the need for a large cross-section. Further studies of the proposed CML VCO were done on 28nm FDSOI in order to reduce the leakage current and increase the switching speed. the same current-starved VCO and CML VCO were implemented on this testchip, and simulations were performed by injecting a double exponential current pulse energy into the previously defined sensitive nodes. The results show SEE sensitivity improvement without narrowing the tuning range or affecting the phase noise response

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

Design and investigation of nanometric and submicron integrated circuits for voltage and digital controlled oscillators

Disertacijoje nagrinėjama LC-ĮVG ir LC-SVG, architektūros, modeliai bei jų kūrimas taikant nanometrines ir submikronines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad tinkamos architektūros parinkimas ir integrinių grandynų technologijų taikymas įgalina sukurti reikiamų parametrų ir kokybės 2–10 GHz įtampa ir skaitmeniniu būdu valdomus generatorius nanometriniuose ir submikroniniuose integriniuose grandynuose. Darbo tikslas – sukurti 2–10 GHz LC-ĮVG ir LC-SVG blokus nanometrinėse bei submikroninėse KMOP integrinių grandynų technologijose, leidžiančius pasiekti reikiamus parametrus skirtus daugiastandarčiams daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams iki 10 GHz. Darbe išspręsti tokie uždaviniai: ištirtos LC-ĮVG ir LC-SVG architektūros skirtingose integrinių grandynų KMOP technologijose ir parinkta optimali architektūra integrinių grandynų sukūrimui, pasiūlytos naujos kokybės funkcijos skirtos LC-ĮVG ir LC-SVG palyginamajai analizei, sukurti ir ištirti LC-ĮVG ir LC-SVG integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatūros ir autoriaus publikacijų disertacijos tema sąrašai ir trys priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašomas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma tyrimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, ginamieji teiginiai. Įvado pabaigoje pristatomos disertacijos tema autoriaus paskelbtos publikacijos ir pranešimai konferencijose bei disertacijos struktūra. Pirmajame skyriuje analizuojamos dažnio generatorių architektūros, jų pritaikymas bei jų pagrindiniai parametrai. Pateikiami pagrindiniai dažnio generatorių parametrai. Apžvelgiamos kokybės funkcijos, nusakančios dažnio generatorių pagrindinius parametrus skirtus palyginamajai analizei. Antrajame skyriuje pateikiamos naujos FOMTT FOMT2 kokybės funkcijos, kuriomis remiantis vertinami valdomo dažnio generatorių pagrindiniai parametrai palyginamajai analizei. Taip pat pateikiami induktyvumo ritės kokybės gerinimo būdai. Trečiajame skyriuje, taikant kompiuterinių skaičiavimų ir eksperimentinius metodus yra kuriami ir tiriami įtampa ir skaitmeniniu būdu valdomų generatorių bei papildomų blokų integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 2 – mokslo žurnaluose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 3 – tarptautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analy-tics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duomenų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti dvylikoje mokslinių konferencijų Lietuvoje ir užsienyje.Disertacij

準ミリ波・ミリ波領域における低位相雑音電圧制御発振器のLC共振器に関する研究

2017岡山県立大学大学