Accelerate & Actualize: Can 2D Materials Bridge the Gap Between Neuromorphic Hardware and the Human Brain?

Two-dimensional (2D) materials present an exciting opportunity for devices and systems beyond the von Neumann computing architecture paradigm due to their diversity of electronic structure, physical properties, and atomically-thin, van der Waals structures that enable ease of integration with conventional electronic materials and silicon-based hardware. All major classes of non-volatile memory (NVM) devices have been demonstrated using 2D materials, including their operation as synaptic devices for applications in neuromorphic computing hardware. Their atomically-thin structure, superior physical properties, i.e., mechanical strength, electrical and thermal conductivity, as well as gate-tunable electronic properties provide performance advantages and novel functionality in NVM devices and systems. However, device performance and variability as compared to incumbent materials and technology remain major concerns for real applications. Ultimately, the progress of 2D materials as a novel class of electronic materials and specifically their application in the area of neuromorphic electronics will depend on their scalable synthesis in thin-film form with desired crystal quality, defect density, and phase purity.Comment: Neuromorphic Computing, 2D Materials, Heterostructures, Emerging Memory Devices, Resistive, Phase-Change, Ferroelectric, Ferromagnetic, Crossbar Array, Machine Learning, Deep Learning, Spiking Neural Network

DEMANDS FOR SPIN-BASED NONVOLATILITY IN EMERGING DIGITAL LOGIC AND MEMORY DEVICES FOR LOW POWER COMPUTING

Miniaturization of semiconductor devices is the main driving force to achieve an outstanding performance of modern integrated circuits. As the industry is focusing on the development of the 3nm technology node, it is apparent that transistor scaling shows signs of saturation. At the same time, the critically high power consumption becomes incompatible with the global demands of sustaining and accelerating the vital industrial growth, prompting an introduction of new solutions for energy efficient computations.Probably the only radically new option to reduce power consumption in novel integrated circuits is to introduce nonvolatility. The data retention without power sources eliminates the leakages and refresh cycles. As the necessity to waste time on initializing the data in temporarily unused parts of the circuit is not needed, nonvolatility also supports an instant-on computing paradigm.The electron spin adds additional functionality to digital switches based on field effect transistors. SpinFETs and SpinMOSFETs are promising devices, with the nonvolatility introduced through relative magnetization orientation between the ferromagnetic source and drain. A successful demonstration of such devices requires resolving several fundamental problems including spin injection from metal ferromagnets to a semiconductor, spin propagation and relaxation, as well as spin manipulation by the gate voltage. However, increasing the spin injection efficiency to boost the magnetoresistance ratio as well as an efficient spin control represent the challenges to be resolved before these devices appear on the market. Magnetic tunnel junctions with large magnetoresistance ratio are perfectly suited as key elements of nonvolatile CMOS-compatible magnetoresistive embedded memory. Purely electrically manipulated spin-transfer torque and spin-orbit torque magnetoresistive memories are superior compared to flash and will potentially compete with DRAM and SRAM. All major foundries announced a near-future production of such memories.Two-terminal magnetic tunnel junctions possess a simple structure, long retention time, high endurance, fast operation speed, and they yield a high integration density. Combining nonvolatile elements with CMOS devices allows for efficient power gating. Shifting data processing capabilities into the nonvolatile segment paves the way for a new low power and high-performance computing paradigm based on an in-memory computing architecture, where the same nonvolatile elements are used to store and to process the information

高密度・高速動作可能なSTT-MRAMへ向けたp-MTJのスイッチング過渡現象とアレイ設計指針に関する研究

Tohoku University遠藤哲郎課

금속산화물 기반 저항변화메모리 소자의 노이즈 특성과 그것의 응용에 관한 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·컴퓨터공학부, 2023. 2. 김재준.In the current pyramid-like structures memory hierarchy, it consists of, from top to bottom, a processing core, cache memory by static random access memory (SRAM), main memory by dynamic random access memory (DRAM), and storage memory by solid-state disk (SSD), or hard disk drive (HDD). In general, the closer to the processing core, the more high-speed operation is required, whereas the farther away from the core, the higher storage capacity is demanded. Consequently, the performance gap between DRAM and NAND Flash memory, which are currently major memory technologies, is continuously increasing. However, the need for new memory technology is increasing in order to solve the problem of data processing speed due to the explosive increase in the amount of data and the physical limitation of the existing memory technologies that has been raised for a long time. In addition, research and development on the storage class memory (SCM) technology is in progress as method of implementing In-Memory Process, a concept to solve the problem of Von Neumann architecture in various research groups. Among the candidates on the SCM, which satisfies both the high speed of DRAM and the density of NAND Flash, the resistive switching random access memory (RRAM) has been widely investigated as a leading candidate for next generation nonvolatile memory applications due to RRAMs advantageous features such as simple structure, low cost, high density, fast operation, and CMOS compatibility. However, the reliability issues which PCM suffered from is also being reproduced in RRAM. RRAMs various issues such as endurance, retention, and uniformity stem from intrinsic variability because resistive switching mechanism of RRAM itself is fundamentally stochastic. The main content of this dissertation is to develop a new electrical analysis technique to improve the reliability of RRAM. First, the elementary low frequency noise (LFN) characteristics of various RRAM devices were analyzed, and the correlation between LFN characteristics and the conduction/resistive switching mechanisms was experimentally verified. Also, it was suggested that the LFN measurement can be an additional analysis technique for devices degradation mechanism and multi-level cell (MLC) operation. Finally, from the random telegraph noise (RTN) measurement, we conducted a study to extract the position and energy of traps that can cause cells failure. The experiment on the extraction of traps physical information using the RTN measurement was conducted for the first in this study, and then research findings provided researchers with guidelines for the RTN analysis of RRAM.현재의 메모리 계층도를 보면 CPU는 고속 동작을 요구하고, 외부메모리는 고용량을 필요로 하기 때문에, 현재의 주요 메모리 기술인 DRAM과 NAND Flash 메모리의 성능 격차는 지속적으로 늘어나고 있다. 하지만 데이터 양의 폭발적인 증가로 인한 데이터 처리 속도 문제, 그리고 오래전부터 제기 되어왔던 기존 메모리의 물리적 한계를 해결하기 위해서 새로운 메모리 기술에 대한 필요성이 증가하고 있다. 또한 기존 폰노이만방식의 컴퓨터 시스템 구조의 문제점을 해결하기 위한 방법인 In-Memory Process를 실현하기 위한 방법으로 DRAM의 high speed, 그리고 NAND Flash의 high density 모두를 만족하는 SCM (storage class memory)기술에 대한 관심이 증가하고 있다. SCM 후보군 중에서, 저항 변화 메모리 소자인 RRAM (Resistive Random Access Memory)은 MIM, cross-point 형태의 간단한 구조를 가지며, 공정 상 집적도 향상에 유리하고, 사용되는 물질이 CMOS공정과 호환 가능하다. 이러한 장점들로 인해 기존 Flash 메모리 소자의 대안으로 학계에서 많은 연구가 진행 되어 왔지만, 한 단계 앞서 연구가 진행되었던 PCM (Phase change RAM)이 겪고 있는 신뢰성 문제가 RRAM에서도 재현되고 있다. RRAM의 신뢰성 문제는 RRAM의 저항 스위칭 메커니즘 자체가 근본적으로 확률적이기 때문에 본질적 변동성에서 기인하는 것이다. 본 논문의 주요 내용은 RRAM의 신뢰성 향상을 위해서 새로운 전기적 분석기법을 개발하는 것이다. 우선 다양한 메커니즘으로 동작하는 RRAM소자의 기본적인 저주파 잡음 특성을 분석하고, 이를 소자의 전도 메커니즘 및 저항 변화 메커니즘과의 연관성을 검증하였다. 측정결과를 기존 저주파 잡음 이론을 통해 해석하고, 다양한 소자에 이를 적용시켜 저주파 잡음 분석 기법이 RRAM의 동작 메커니즘 분석에 이용할 수 있음을 증명하였다. 또한, 소자의 열화 메커니즘 및 MLC (Multi-Level Cell) 분석에 있어서도 저주파 잡음 측정이 추가적인 분석기법이될 수 있음을 제시하였다. 마지막으로, 소자의 저주파 잡음 특성 중 하나인 RTN (Random Telegraph Noise)특성 분석을 통해 셀의 fail 을 일으킬 수 있는 trap의 위치 및 에너지를 추출하는 연구를 진행하였다. RRAM의 trap정보 추출에 관한 측정 및 분석은 본 연구에서 최초로 진행되었던 것이고, 이후 RRAM의 RTN분석에 가이드라인을 제시하였다.Chapter1 Introduction 1 1.1 Memory trends 1 1.1.1 Memory wall 1 1.1.2 In-memory processing 3 1.2 SCM technologies 4 1.2.1 Phase change memory 4 1.2.2 Magnetic memory 6 1.2.3 Ferroelectric memory 7 1.2.4 Resistive memory 8 1.3 Thesis content overview 12 1.3.1 Thesis objectives 12 1.3.2 Thesis outline 13 Chapter2 Overview on conduction mechanisms 14 2.1 Electrode-limited conduction mechanisms 14 2.1.1 Schottky emission 15 2.1.2 Fowler-Nordheim (F-N) and direct tunneling 17 2.2 Bulk-limited conduction mechanisms 18 2.2.1 Poole-Frenkel (P-F) emission 18 2.2.2 Ohmic conduction 19 2.2.3 Space charge limited conduction (SCLC) 20 Chapter3 LFN applications for RRAM analysis 23 3.1 Introduction to 1/f 23 3.2 LFN application (1): Resistive switching analysis 26 3.3 LFN application (2): MLC analysis 30 3.4 LFN application (3): Degradation analysis 35 Chapter4 Analysis of conduction mechanism using LFN 39 4.1 Thermochemical mechanism RRAM 39 4.1.1 Fabrication 39 4.1.2 Experimental results: RS and I-V characteristics 40 4.1.3 Experimental results: LFN characteristics 46 4.2 Valence change mechanism RRAM 50 4.2.1 Fabrication 50 4.2.2 Experimental results: RS and I-V characteristics 52 4.2.3 Experimental results: LFN characteristics 55 4.3 Comparative analysis of conduction mechanism 58 4.3.1 Fabrication 58 4.3.2 Experimental results: RS and I-V characteristics 61 4.3.3 Experimental results: LFN characteristics 63 Chapter5 Random telegraph noise (RTN) in RRAM 67 5.1 Introduction to RTN 67 5.2 RTN in RRAM 69 5.2.1 Methodology for extracting trap information 69 5.2.2 Experimental results 73 Chapter6 78 Conclusions 78박

Magnetic racetrack memory: from physics to the cusp of applications within a decade

Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today's technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent developments, RTM has attracted the attention of the computer architecture community that has evaluated the use of RTM at various levels in the memory stack. Recent studies advocate RTM as a promising compromise between, on the one hand, power-hungry, volatile memories and, on the other hand, slow, nonvolatile storage. By optimizing the memory subsystem, significant performance improvements can be achieved, enabling a new era of cache, graphical processing units, and high capacity memory devices. In this article, we provide an overview of the major developments of RTM technology from both the physics and computer architecture perspectives over the past decade. We identify the remaining challenges and give an outlook on its future