A single-chip NMOS analog front-end LSI for modems

金沢大学理工研究域　電子情報学系This paper presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCF\u27s, an agc circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 mu m line double polysilicon gate NMOS process. Chip size is 7. 14 multiplied by 6. 51 mm. The circuit operates on plus or minus 5 v power supplies. Typical power consumption is 270 mw. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size

24- and 120-chanell transmultiplexers built with new digital signal processing LSI\u27s

金沢大学大学院自然科学研究科情報システム金沢大学工学部Two new digital transmultiplexers intended for commerical use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel FDM group signals and a 24-channel PCM carrier signal. The other mutually connects two 60-channel FDM supergroup signals and five 24-channel or four 30-channel PCM signals. Both exploit a block processing digital SSB-FDM multiplex/demultiplex scheme employing a cascade of an FFT processor and a set of complex coefficient digital filters. They have been built using newly developed high-level DSP LSI chips. Algorithmic considerations, developed LSI architecture, and equipment configuration are described as well as digital processor design details and measured performance

A single-chip NMOS analog front-end LSI for modems

金沢大学大学院自然科学研究科情報システム金沢大学工学部This paper presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCF\u27s, an agc circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 mu m line double polysilicon gate NMOS process. Chip size is 7. 14 multiplied by 6. 51 mm. The circuit operates on plus or minus 5 v power supplies. Typical power consumption is 270 mw. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size

Application of LSI to signal detection: The deltic DFPCC

The development of the DELTIC DFPCC serial mode signal processor is discussed. The processor is designed to detect in the presence of background noise a signal coded into the zero crossings of the waveform. The unique features of the DELTIC DFPCC include versatility in handling a variety of signals and relative simplicity in implementation. A theoretical performance model is presented which predicts the expected value of the output signal as a function of the input signal to noise ratio. Experimental results obtained with the prototype system, which was breadboarded with LSI, MSI and SSI components, are given. The device was compared with other LSI schemes for signal processing and it was concluded that the DELTIC DFPCC is simpler and in some cases more versatile than other systems. With established LSI technology, low frequency systems applicable to sonar and similar problems are feasible

Data processor with conditionally supplied clock signals

Parallel data processor clock pulses are conditionally supplied to processing unit in response to relative values of binary bit of control source and binary bit derived on single lead. Use of single lead simplifies fabrication of large-scale integrated networks

Real-Time Vocal Tract Modelling

To date, most speech synthesis techniques have relied upon the representation of the vocal tract by some form of filter, a typical example being linear predictive coding (LPC). This paper describes the development of a physiologically realistic model of the vocal tract using the well-established technique of transmission line modelling (TLM). This technique is based on the principle of wave scattering at transmission line segment boundaries and may be used in one, two, or three dimensions. This work uses this technique to model the vocal tract using a one-dimensional transmission line. A six-port scattering node is applied in the region separating the pharyngeal, oral, and the nasal parts of the vocal tract

Second year technical report on-board processing for future satellite communications systems

Advanced baseband and microwave switching techniques for large domestic communications satellites operating in the 30/20 GHz frequency bands are discussed. The nominal baseband processor throughput is one million packets per second (1.6 Gb/s) from one thousand T1 carrier rate customer premises terminals. A frequency reuse factor of sixteen is assumed by using 16 spot antenna beams with the same 100 MHz bandwidth per beam and a modulation with a one b/s per Hz bandwidth efficiency. Eight of the beams are fixed on major metropolitan areas and eight are scanning beams which periodically cover the remainder of the U.S. under dynamic control. User signals are regenerated (demodulated/remodulated) and message packages are reformatted on board. Frequency division multiple access and time division multiplex are employed on the uplinks and downlinks, respectively, for terminals within the coverage area and dwell interval of a scanning beam. Link establishment and packet routing protocols are defined. Also described is a detailed design of a separate 100 x 100 microwave switch capable of handling nonregenerated signals occupying the remaining 2.4 GHz bandwidth with 60 dB of isolation, at an estimated weight and power consumption of approximately 400 kg and 100 W, respectively

Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

Chip level simulation of fault tolerant computers

Chip level modeling techniques, functional fault simulation, simulation software development, a more efficient, high level version of GSP, and a parallel architecture for functional simulation are discussed