A phase-locked frequency divide-by-3 optical parametric oscillator

Accurate phase-locked 3:1 division of an optical frequency was achieved, by using a continuous-wave (cw) doubly resonant optical parametric oscillator. A fractional frequency stability of 2*10^(-17) of the division process has been achieved for 100s integration time. The technique developed in this work can be generalized to the accurate phase and frequency control of any cw optical parametric oscillator.Comment: 4 pages, 5 figures in a postscript file. To appear in a special issue of IEEE Trans. Instr. & Meas., paper FRIA-2 presented at CPEM'2000 conference, Sydney, May 200

DSN radio science system design and testing for Voyager-Neptune encounter

The Deep Space Network (DSN) Radio Science System presently implemented within the Deep Space Network was designed to meet stringent requirements imposed by the demands of the Voyager-Neptune encounter and future missions. One of the initial parameters related to frequency stability is discussed. The requirement, specification, design, and methodology for measuring this parameter are described. A description of special instrumentation that was developed for the test measurements and initial test data resulting from the system tests performed at Canberra, Australia and Usuda, Japan are given

DESIGN COMMON MODE LOGIC (CML) FREQUENCY DIVIDER IN CMOSPORCESSTECHNOLOGY

The objective of this project is to design current mode logic (CML) frequency divider in CMOS technology. The current spikes that occur during transition between tacking and latch mode in transistor will degrade the performance of the frequency divider. The parasitic capacitances that exist in two transistor of tracking circuit directly contribute to the latch delay. The fundamental of this project is to understand the basic operation of CML of D Flip-flop based frequency divider. The new circuit which known as modified frequency divider is designed in order to overcome the current spike that occur during the transition between track and latch mode hence to reduce the rise time and fall time at the output. The modified frequency divider is able to reduce 20% up until 57.14% of the current spike that occurs during the transition between the track and latch mode. It also managed to reduce 11.76% up until 53.85% of the rise time and fall time at the output voltage hence reduce the latch delay

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

An Ultra-Stable Referenced Interrogation System in the Deep Ultraviolet for a Mercury Optical Lattice Clock

We have developed an ultra-stable source in the deep ultraviolet, suitable to fulfill the interrogation requirements of a future fully-operational lattice clock based on neutral mercury. At the core of the system is a Fabry-P\'erot cavity which is highly impervious to temperature and vibrational perturbations. The mirror substrate is made of fused silica in order to exploit the comparatively low thermal noise limits associated with this material. By stabilizing the frequency of a 1062.6 nm Yb-doped fiber laser to the cavity, and including an additional link to LNE-SYRTE's fountain primary frequency standards via an optical frequency comb, we produce a signal which is both stable at the 1E-15 level in fractional terms and referenced to primary frequency standards. The signal is subsequently amplified and frequency-doubled twice to produce several milliwatts of interrogation signal at 265.6 nm in the deep ultraviolet.Comment: 7 pages, 6 figure

ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE

Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide injection bandwidth, so that the jitter performance of the mmW-band output signals is determined by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively. However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented. At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter, mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.clos

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Realization of the farad from the dc quantum Hall effect with digitally-assisted impedance bridges

A new traceability chain for the derivation of the farad from dc quantum Hall effect has been implemented at INRIM. Main components of the chain are two new coaxial transformer bridges: a resistance ratio bridge, and a quadrature bridge, both operating at 1541 Hz. The bridges are energized and controlled with a polyphase direct-digital-synthesizer, which permits to achieve both main and auxiliary equilibria in an automated way; the bridges and do not include any variable inductive divider or variable impedance box. The relative uncertainty in the realization of the farad, at the level of 1000 pF, is estimated to be 64E-9. A first verification of the realization is given by a comparison with the maintained national capacitance standard, where an agreement between measurements within their relative combined uncertainty of 420E-9 is obtained.Comment: 15 pages, 11 figures, 3 table

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the\ud proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms

Advanced tracking and data relay experiments study: Multimode transponder experiment equipment

Plans and implementation concepts were developed for a series of experiments utilizing a Multimode Transponder mounted in an aircraft working either through a spacecraft or directly with a ground station which would simulate a TDRSS user working through the TDRSS. The purpose of the experiments is to determine the best modulation and encoding techniques for combating RFI in discreet bands. The experiments also determine the feasibility and accuracy of range and range rate measurements with the various modulation and encoding techniques. An analysis of the Multimode Transponder and ground support equipment is presented, and the additional equipment required to perform the experiments described above is determined