Silicon Photonic Platforms and Systems for High-speed Communications

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform

Wireless Testing of Integrated Circuits.

Integrated circuits (ICs) are usually tested during manufacture by means of automatic testing equipment (ATE) employing probe cards and needles that make repeated physical contact with the ICs under test. Such direct-contact probing is very costly and imposes limitations on the use of ATE. For example, the probe needles must be frequently cleaned or replaced, and some emerging technologies such as three-dimensional ICs cannot be probed at all. As an alternative to conventional probe-card testing, wireless testing has been proposed. It mitigates many of the foregoing problems by replacing probe needles and contact points with wireless communication circuits. However, wireless testing also raises new problems which are poorly understood such as: What is the most suitable wireless communication technique to employ, and how well does it work in practice? This dissertation addresses the design and implementation of circuits to support wireless testing of ICs. Various wireless testing methods are investigated and evaluated with respect to their practicality. The research focuses on near-field capacitive communication because of its efficiency over the very short ranges needed during IC manufacture. A new capacitive channel model including chip separation, cross-talk, and misalignment effects is proposed and validated using electro-magnetic simulation studies to provide the intuitions for efficient antenna and circuit design. We propose a compact clock and data recovery architecture to avoid a dedicated clock channel. An analytical model which predicts the DC-level fluctuation due to the capacitive channel is presented. Based on this model, feed-forward clock selection is designed to enhance performance. A method to select proper channel termination is discussed to maximize the channel efficiency for return-to-zero signaling. Two prototype ICs incorporating wireless testing systems were fabricated and tested with the proposed methods of testing digital circuits. Both successfully demonstrated gigahertz communication speeds with a bit-error rate less than 10^−11. A third prototype IC containing analog voltage measurement circuits was implemented to determine the feasibility of wirelessly testing analog circuits. The fabricated prototype achieved satisfactory voltage measurement with 1 mV resolution. Our work demonstrates the validity of the proposed models and the feasibility of near-field capacitive communication for wireless testing of ICs.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/93993/1/duelee_1.pd

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional clock distribution schemes. These networks utilize ad- ditional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. Contactless test has been considered as an alternative for conventional test methods. This paper, consequently, introduces a design method- ology for resonant 3-D clock networks that supports wireless pre- bond testing through the use of inductive links. By employing the inductors comprising the LC tanks of the resonant clock net- works as the receiver circuit for the links, the need for additional circuits and/or interconnect resources during pre-bond test is essentially eliminated. The proposed technique produces low power and pre-bond testable 3-D clock distribution networks. Simulation results indicate 98.5% and 99% decrease in the area overhead and power consumed by the contactless testing method as compared to existing methods

소형동물의 뇌신경 자극을 위한 완전 이식형 신경자극기

학위논문(박사)--서울대학교 대학원 :공과대학 전기·정보공학부,2020. 2. 김성준.In this study, a fully implantable neural stimulator that is designed to stimulate the brain in the small animal is described. Electrical stimulation of the small animal is applicable to pre-clinical study, and behavior study for neuroscience research, etc. Especially, behavior study of the freely moving animal is useful to observe the modulation of sensory and motor functions by the stimulation. It involves conditioning animal's movement response through directional neural stimulation on the region of interest. The main technique that enables such applications is the development of an implantable neural stimulator. Implantable neural stimulator is used to modulate the behavior of the animal, while it ensures the free movement of the animals. Therefore, stable operation in vivo and device size are important issues in the design of implantable neural stimulators. Conventional neural stimulators for brain stimulation of small animal are comprised of electrodes implanted in the brain and a pulse generation circuit mounted on the back of the animal. The electrical stimulation generated from the circuit is conveyed to the target region by the electrodes wire-connected with the circuit. The devices are powered by a large battery, and controlled by a microcontroller unit. While it represents a simple approach, it is subject to various potential risks including short operation time, infection at the wound, mechanical failure of the device, and animals being hindered to move naturally, etc. A neural stimulator that is miniaturized, fully implantable, low-powered, and capable of wireless communication is required. In this dissertation, a fully implantable stimulator with remote controllability, compact size, and minimal power consumption is suggested for freely moving animal application. The stimulator consists of modular units of surface-type and depth-type arrays for accessing target brain area, package for accommodating the stimulating electronics all of which are assembled after independent fabrication and implantation using customized flat cables and connectors. The electronics in the package contains ZigBee telemetry for low-power wireless communication, inductive link for recharging lithium battery, and an ASIC that generates biphasic pulse for neural stimulation. A dual-mode power-saving scheme with a duty cycling was applied to minimize the power consumption. All modules were packaged using liquid crystal polymer (LCP) to avoid any chemical reaction after implantation. To evaluate the fabricated stimulator, wireless operation test was conducted. Signal-to-Noise Ratio (SNR) of the ZigBee telemetry were measured, and its communication range and data streaming capacity were tested. The amount of power delivered during the charging session depending on the coil distance was measured. After the evaluation of the device functionality, the stimulator was implanted into rats to train the animals to turn to the left (or right) following a directional cue applied to the barrel cortex. Functionality of the device was also demonstrated in a three-dimensional maze structure, by guiding the rats to navigate better in the maze. Finally, several aspects of the fabricated device were discussed further.본 연구에서는 소형 동물의 두뇌를 자극하기 위한 완전 이식형 신경자극기가 개발되었다. 소형 동물의 전기자극은 전임상 연구, 신경과학 연구를 위한 행동연구 등에 활용된다. 특히, 자유롭게 움직이는 동물을 대상으로 한 행동 연구는 자극에 의한 감각 및 운동 기능의 조절을 관찰하는 데 유용하게 활용된다. 행동 연구는 두뇌의 특정 관심 영역을 직접적으로 자극하여 동물의 행동반응을 조건화하는 방식으로 수행된다. 이러한 적용을 가능케 하는 핵심기술은 이식형 신경자극기의 개발이다. 이식형 신경자극기는 동물의 움직임을 방해하지 않으면서도 그 행동을 조절하기 위해 사용된다. 따라서 동물 내에서의 안정적인 동작과 장치의 크기가 이식형 신경자극기를 설계함에 있어 중요한 문제이다. 기존의 신경자극기는 두뇌에 이식되는 전극 부분과, 동물의 등 부분에 위치한 회로부분으로 구성된다. 회로에서 생산된 전기자극은 회로와 전선으로 연결된 전극을 통해 목표 지점으로 전달된다. 장치는 배터리에 의해 구동되며, 내장된 마이크로 컨트롤러에 의해 제어된다. 이는 쉽고 간단한 접근방식이지만, 짧은 동작시간, 이식부위의 감염이나 장치의 기계적 결함, 그리고 동물의 자연스러운 움직임 방해 등 여러 문제점을 야기할 수 있다. 이러한 문제의 개선을 위해 무선통신이 가능하고, 저전력, 소형화된 완전 이식형 신경자극기의 설계가 필요하다. 본 연구에서는 자유롭게 움직이는 동물에 적용하기 위하여 원격 제어가 가능하며, 크기가 작고, 소모전력이 최소화된 완전이식형 자극기를 제시한다. 설계된 신경자극기는 목표로 하는 두뇌 영역에 접근할 수 있는 표면형 전극과 탐침형 전극, 그리고 자극 펄스 생성 회로를 포함하는 패키지 등의 모듈들로 구성되며, 각각의 모듈은 독립적으로 제작되어 동물에 이식된 뒤 케이블과 커넥터로 연결된다. 패키지 내부의 회로는 저전력 무선통신을 위한 지그비 트랜시버, 리튬 배터리의 재충전을 위한 인덕티브 링크, 그리고 신경자극을 위한 이상성 자극파형을 생성하는 ASIC으로 구성된다. 전력 절감을 위해 두 개의 모드를 통해 사용률을 조절하는 방식이 장치에 적용된다. 모든 모듈들은 이식 후의 생물학적, 화학적 안정성을 위해 액정 폴리머로 패키징되었다. 제작된 신경자극기를 평가하기 위해 무선 동작 테스트가 수행되었다. 지그비 통신의 신호 대 잡음비가 측정되었으며, 해당 통신의 동작거리 및 데이터 스트리밍 성능이 검사되었고, 장치의 충전이 수행될 때 코일간의 거리에 따라 전송되는 전력의 크기가 측정되었다. 장치의 평가 이후, 신경자극기는 쥐에 이식되었으며, 해당 동물은 이식된 장치를 이용해 방향 신호에 따라 좌우로 이동하도록 훈련되었다. 또한, 3차원 미로 구조에서 쥐의 이동방향을 유도하는 실험을 통하여 장치의 기능성을 추가적으로 검증하였다. 마지막으로, 제작된 장치의 특징이 여러 측면에서 심층적으로 논의되었다.Chapter 1 : Introduction 1 1.1. Neural Interface 2 1.1.1. Concept 2 1.1.2. Major Approaches 3 1.2. Neural Stimulator for Animal Brain Stimulation 5 1.2.1. Concept 5 1.2.2. Neural Stimulator for Freely Moving Small Animal 7 1.3. Suggested Approaches 8 1.3.1. Wireless Communication 8 1.3.2. Power Management 9 1.3.2.1. Wireless Power Transmission 10 1.3.2.2. Energy Harvesting 11 1.3.3. Full implantation 14 1.3.3.1. Polymer Packaging 14 1.3.3.2. Modular Configuration 16 1.4. Objectives of This Dissertation 16 Chapter 2 : Methods 18 2.1. Overview 19 2.1.1. Circuit Description 20 2.1.1.1. Pulse Generator ASIC 21 2.1.1.2. ZigBee Transceiver 23 2.1.1.3. Inductive Link 24 2.1.1.4. Energy Harvester 25 2.1.1.5. Surrounding Circuitries 26 2.1.2. Software Description 27 2.2. Antenna Design 29 2.2.1. RF Antenna 30 2.2.1.1. Design of Monopole Antenna 31 2.2.1.2. FEM Simulation 31 2.2.2. Inductive Link 36 2.2.2.1. Design of Coil Antenna 36 2.2.2.2. FEM Simulation 38 2.3. Device Fabrication 41 2.3.1. Circuit Assembly 41 2.3.2. Packaging 42 2.3.3. Electrode, Feedthrough, Cable, and Connector 43 2.4. Evaluations 45 2.4.1. Wireless Operation Test 46 2.4.1.1. Signal-to-Noise Ratio (SNR) Measurement 46 2.4.1.2. Communication Range Test 47 2.4.1.3. Device Operation Monitoring Test 48 2.4.2. Wireless Power Transmission 49 2.4.3. Electrochemical Measurements In Vitro 50 2.4.4. Animal Testing In Vivo 52 Chapter 3 : Results 57 3.1. Fabricated System 58 3.2. Wireless Operation Test 59 3.2.1. Signal-to-Noise Ratio Measurement 59 3.2.2. Communication Range Test 61 3.2.3. Device Operation Monitoring Test 62 3.3. Wireless Power Transmission 64 3.4. Electrochemical Measurements In Vitro 65 3.5. Animal Testing In Vivo 67 Chapter 4 : Discussion 73 4.1. Comparison with Conventional Devices 74 4.2. Safety of Device Operation 76 4.2.1. Safe Electrical Stimulation 76 4.2.2. Safe Wireless Power Transmission 80 4.3. Potential Applications 84 4.4. Opportunities for Further Improvements 86 4.4.1. Weight and Size 86 4.4.2. Long-Term Reliability 93 Chapter 5 : Conclusion 96 Reference 98 Appendix - Liquid Crystal Polymer (LCP) -Based Spinal Cord Stimulator 107 국문 초록 138 감사의 글 140Docto

Development of micromachined millimeter-wave modules for next-generation wireless transceiver front-ends

This thesis discusses the design, fabrication, integration and characterization of millimeter wave passive components using polymer-core-conductor surface micromachining technologies. Several antennas, including a W-band broadband micromachined monopole antenna on a lossy glass substrate, and a Ka-band elevated patch antenna, and a V-band micromachined horn antenna, are presented. All antennas have advantages such as a broad operation band and high efficiency. A low-loss broadband coupler and a high-Q cavity for millimeter-wave applications, using surface micromachining technologies is reported using the same technology. Several low-loss all-pole band-pass filters and transmission-zero filters are developed, respectively. Superior simulation and measurement results show that polymer-core-conductor surface micromachining is a powerful technology for the integration of high-performance cavity, coupler and filters. Integration of high performance millimeter-wave transceiver front-end is also presented for the first time. By elevating a cavity-filter-based duplexer and a horn antenna on top of the substrate and using air as the filler, the dielectric loss can be eliminated. A full-duplex transceiver front-end integrated with amplifiers are designed, fabricated, and comprehensively characterized to demonstrate advantages brought by this surface micromachining technology. It is a low loss and substrate-independent solution for millimeter-wave transceiver integration.Ph.D.Committee Chair: John Papapolymerou; Committee Chair: Manos Tentzeris; Committee Member: Gordon Stuber; Committee Member: John Cressler; Committee Member: John Z. Zhang; Committee Member: Joy Laska

Compact and Efficient Millimetre-Wave Circuits for Wideband Applications

Radio systems, along with the ever increasing processing power provided by computer technology, have altered many aspects of our society over the last century. Various gadgets and integrated electronics are found everywhere nowadays; many of these were science-fiction only a few decades ago. Most apparent is perhaps your ``smart phone'', possibly kept within arm's reach wherever you go, that provides various services, news updates, and social networking via wireless communications systems. The frameworks of the fifth generation wireless system is currently being developed worldwide. Inclusion of millimetre-wave technology promise high-speed piconets, wireless back-haul on pencil-beam links, and further functionality such as high-resolution radar imaging. This thesis addresses the challenge to provide signals at carrier frequencies in the millimetre-wave spectrum, and compact integrated transmitter front-ends of sub-wavelength dimensions. A radio frequency pulse generator, i.e. a ``wavelet genarator'', circuit is implemented using diodes and transistors in III--V compound semiconductor technology. This simple but energy-efficient front-end circuit can be controlled on the time-scale of picoseconds. Transmission of wireless data is thereby achieved at high symbol-rates and low power consumption per bit. A compact antenna is integrated with the transmitter circuit, without any intermediate transmission line. The result is a physically small, single-chip, transmitter front-end that can output high equivalent isotropically radiated power. This element radiation characteristic is wide-beam and suitable for array implementations

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system