60 research outputs found
Development of a Low-Noise High Common-Mode-Rejection Instrumentation Amplifier
Several previously used instrumentation amplifier circuits were examined to find limitations and possibilities for improvement. One general configuration is analyzed in detail, and methods for improvement are enumerated. An improved amplifier circuit is described and analyzed with respect to common mode rejection and noise. Experimental data are presented showing good agreement between calculated and measured common mode rejection ratio and equivalent noise resistance. The amplifier is shown to be capable of common mode rejection in excess of 140 db for a trimmed circuit at frequencies below 100 Hz and equivalent white noise below 3.0 nv/square root of Hz above 1000 Hz
New mathematical formulation for designing a fully differential self-biased folded cascode amplifier
One of the most important building blocks in analog circuit design is the operational amplifiers. This is because of their versatility and wide spread usage in many applications such as communications transmitters and receivers, analog to digital converters, or any other application that requires a small signal to be amplified. The basic amplifier topologies are introduced. Then, some operational amplifiers topologies are introduced with some techniques to self bias these amplifiers. The folded cascode fully differential Op-Amp with self bias is presented. This is one of the newest amplifier topologies which provide stable self-biased amplifiers. A new mathematical model for fully differential folded cascode amplifiers is presented and generalized to include the family of fully differential complementary amplifiers. This formulation focuses on deriving detailed design equations for the amplifier gain and frequency response. The equations are verified through time domain and frequency domain simulations of different fabrication processes to ensure the validity of the model across a wide range of processes. The model was verified against TMSC 180nm, 250nm, and 350nm fabrication processes. The new model agrees well with simulations; with 1% error for the amplifier gain and \u3c7% error for amplifier bandwidth. The relatively high error value for the bandwidth is because the model considers the worst case scenario and overestimates the output capacitance. Finally, the algorithm of getting this formulation is extended to include special and commonly used cases. This formulation proved to be very useful in designing stable, self-biased, fully differential folded cascode amplifiers
Novel approaches in current-feedback operational amplifier design
The aim of this research programme was to design and develop a novel bipolar
junction transistor Current Feedback Operational Amplifier (CFOA) with a good
Common-Mode Rejection Ratio (CMRR), suitable for radio frequency (RF)
applications. This research focused on investigation of the established CFOA with
the emphases of improving CMRR, bandwidth, Voltage-Offset and Slew-rate
performance. The majority of the results of this work have been reported by the
author in references [11 to [6].
Initially a thorough analysis of the conventional CFOA was undertaken to provide an
in depth understanding of the amplifier's operation, and this work revealed that the
main shortcomings of the CFOA are in the design of the input stage. This initial
study focussed on establishing reasons for the poor DC offset-voltage performance
and CMRR and confirmed that these designs have inherently poor performance in
these two elements. The analysis was carried out using both theoretical modelling
and computer simulation.
Using this analysis of the conventional CFOA as a benchmark, various novel circuit
techniques were investigated. Several new input circuits for the CFOA were
proposed with respect to improving the three previously mentioned key
characteristics, viz., CMRR, offset voltage, and slew-rate. The first technique
explored is based on floating the entire input stage of the CFOA which yielded
significant improvements in CMRR, Offset-Voltage and bandwidth, and the results of
this workwere published in [11, [2], and P). Based on these initial findings a second
major development was undertaken. This time a bootstrapping technique was
employed to key sections of the input stage, leading to new, simplified input circuit
topology. This development leads to low DC offset voltage, wide bandwidth and high
CNIRR, as well as improved gain accuracy, and was published by the author in [4,5].
A logical approach to the different input stage architectures examined by the author
resulted in identification of a hierarchy of 6 different input CFOA circuit designs and
a comparative study was undertaken showing their relative performance in respect of
CMRR, Offset-Voltage and Slew-rate. This work was presented by the author, [6]
Automated design synthesis of CMOS operational amplifers
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 159-161).by Ognen J. Nastov.M.S
Wide-Bandwidth CFOA with High CMRR Performance
In this paper the authors analyze the conventional current-feedback operational amplifier (CFOA) in terms of common-mode-rejection ratio (CMRR) performance, and having identified the mechanism primarily responsible for the CMRR, they propose two new architecture CFOAs. These new CFOAs are further developed, and modified to provide improved bandwidth, AC gain accuracy and high CMRR performance. The key features of the two proposed new CFOAs are the designs of the internal voltage followers which have two separate biasing currents with a similar dynamic architecture to that of the conventional CFOA. The magnitude of one bias current determines the value of the maximum CMRR, and the second can be used to maximize bandwidth
Physical design of low power operational amplifier
A CMOS single output two stage operational amplifier is presented which operates at 3 V power supply at 0.18 micron (i.e., 180 nm) technology. It is designed to meet a set of provided specifications. The unique behavior of the MOS transistors in sub- threshold region not only allows a designer to work at low input bias current but also at low voltage. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 20.4dB and a -3db bandwidth of 202 kHz and a unity gain bandwidth of 2.15MHz for a load of 5 pF capacitor. This op-amp has a PSRR (+) of 85.0 dB and a PSRR (-) of 60.0 dB. It has a CMRR (dc) of -64.4 dB, and an output slew rate of 12.465 v/µs. The power consumption for the op-amp is 1.18mW. The presented op-amp has a Input Common Mode Range(ICMR) of -1V to 2.4V. The op-amp is designed in the 180 nm technology using the umc 180 nm technology library. The layout for the above op-amp had been designed and the post layout simulations are compared with the schematic simulations.
The proposed op-amp is a simple two stage single ended op-amp. The input stage of the op-amp is a differential amplifier with an NMOS pair. The second stage of the op-amp is a simple PMOS common source amplifier. The second stage is used to increase the voltage swing at the output. The op-amp uses a -3v Vdd and a -3v Vss and consumes a power of around 0.6mW (as per post layout simulations)
First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS
We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth
CMOS low voltage preamplifier based on 1/F noise cancellation
Noise in CMOS integrated circuits -- Noise sources in MOSFET transistors- -- Low noise techniques -- Chopper stabilization technique -- A CHS behavior model in MATLAB/SIMULINK -- Supplemental analysis of CHS -- Low voltage operation & elementary circuits -- Voltage requirements of analog circuits -- Basic circuits and functions -- Implementation of the CHS modules -- Noise in cascaded stages -- Modulators -- Selective amplifier -- Automatic tuning & machine oscillator -- Simulation results and experimental prototype
QUBIT COUPLED MECHANICAL RESONATOR IN AN ELECTROMECHANICAL SYSTEM
This thesis describes the development of a hybrid quantum electromechanical system. In this system the mechanical resonator is capacitively coupled to a superconducting transmon which is embedded in a superconducting coplanar waveguide (CPW) cavity. The difficulty of achieving high quality of superconducting qubit in a high-quality voltage-biased cavity is overcome by integrating a superconducting reflective T-filter to the cavity. Further spectroscopic and pulsed measurements of the hybrid system demonstrate interactions between the ultra-high frequency mechanical resonator and transmon qubit. The noise of mechanical resonator close to ground state is measured by looking at the spectroscopy of the transmon. At last, fabrication and tests of membrane resonators are discussed
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