1.5 Gbit/s FPGA implementation of a fully-parallel turbo decoder designed for mission-critical machine-type communication applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying Logarithmic Bahl-Cocke-Jelinek-Raviv (Log- BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of realtime wireless communication schemes. Motivated by this, we recently proposed a Fully Parallel Turbo Decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for Field-Programmable Gate Array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gbit/s and an average latency of 0.56 s, when decoding frames comprising N=720 bits. These are respectively 13.2 times and 11.1 times superior to those of the state-of-the- art FPGA implementation of the Log-BCJR Long- Term Evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 kALUTs Mbit/s , which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest N=40-bit LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mbit/s and an average latency of 0.18 s, which are respectively 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 kALUTs Mbit/s is 146.4 times superior to that of the benchmarker decoder

An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes

Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 us, achieving a throughput of 27MbpsComment: 4 pages, 4 figures, 4 tables, Published in 27th International Conference on Field Programmable Logic and Applications (FPL), 201

Hardware implementation of multiple-input multiple-output transceiver for wireless communication

This dissertation proposes an efficient hardware implementation scheme for iterative multi-input multi-output orthogonal frequency-division multiplexing (MIMO-OFDM) transceiver. The transmitter incorporates linear precoder designed with instantaneous channel state information (CSI). The receiver implements MMSE-IC (minimum mean square error interference cancelation) detector, channel estimator, low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses QR decomposition (QRD) of complex-valued matrices with four co-ordinate rotation digital computer (CORDIC) cores and back substitution to achieve the best tradeoff between resource and throughput. The MIMO system is used in field test and the results indicate that the instantaneous CSI varies very fast in practices and the performance of linear precoder designed with instantaneous CSI is limited. Instead, statistic CSI had to be used. This dissertation also proposes a higher-rank principle Kronecker model (PKM). That exploits the statistic CSI to simulate the fading channels. The PKM is constructed by decomposing the channel correlation matrices with the higher-order singular value decomposition (HOSVD) method. The proposed PKM-HOSVD model is validated by extensive field experiments conducted for 4-by-4 MIMO systems in both indoor and outdoor environments. The results confirm that the statistic CSI varies slowly and the PKM-HOSVD will be helpful in the design of linear precoders. --Abstract, page iv

An improved algorithm of generating shortening patterns for polar codes

The rate matching in polar codes becomes a solution when non-conventional codewords of length N≠2n are required. Shortening is employed to design arbitrary rate codes from a mother code with a given rate. Based on the conventional shortening scheme, length of constructed polar codes is limited. In this paper, we demonstrate the presence of favorable and unfavorable shortening patterns. The structure of polar codes is leveraged to eliminate unfavorable shortening patterns, thereby reducing the search space. We generate an auxiliary matrix through likelihood and subsequently select the shortening bits from the matrix. Unlike different existing methods that offer only a single shortening pattern, our algorithm generates multiple favorable shortening patterns, encompassing all possible favorable configurations. This algorithm has a reduced complexity and suboptimal performance, effectively identifying shortening patterns and sets of frozen symbols for any polar code. Simulation results underscore that the shortened polar codes exhibit performance closely aligned with the mother codes. Our algorithm addresses this security concern by making it more difficult for an attacker to obtain the information set and frozen symbols of a polar code. This is done by generating multiple shortening patterns for any polar code

Digital VLSI Architectures for Advanced Channel Decoders

Error-correcting codes are strongly adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probes. New and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. This work aims to focus on Polar codes, which are a recent class of channel codes with the proven ability to reduce decoding error probability arbitrarily small as the block-length is increased, provided that the code rate is less than the capacity of the channel. This property and the recursive code-construction of this algorithms attracted wide interest from the communications community. Hardware architectures with reduced complexity can efficiently implement a polar codes decoder using either successive cancellation approximation or belief propagation algorithms. The latter offers higher throughput at high signal-to-noise ratio thanks to the inherently parallel decision-making capability of such decoder type. A new analysis on belief propagation scheduling algorithms for polar codes and on interconnection structure of the decoding trellis not covered in literature is also presented. It allowed to achieve an hardware implementation that increase the maximum information throughput under belief propagation decoding while also minimizing the implementation complexity

Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: a tutorial and design example

Channel codes such as Low-Density Parity-Check (LDPC) codes may be employed in wireless communication schemes for correcting transmission errors. This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. However, this LDPC decoding operation is associated with a potentially inadequate processing throughput, which may constrain the attainable transmission throughput. In order to increase the processing throughput, the clock period may be reduced, albeit this is at the cost of potentially introducing timing errors. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting not only transmission errors, but also timing errors, even without the requirement for additional circuitry. Motivated by this, we provide the first comprehensive tutorial on LDPC-SDs. We also propose a novel design flow for timing-error-tolerant LDPC decoders. We use this to develop a timing error model for LDPC-SDs and investigate how their overall error correction performance is affected by overclocking. Drawing upon our findings, we propose a modified LDPC-SD, having an improved timing error tolerance. In a particular practical scenario, this modification eliminates the approximately 1 dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD

Fragile boundaries of tailored surface codes

Biased noise is common in physical qubits, and tailoring a quantum code to the bias by locally modifying stabilizers or changing boundary conditions has been shown to greatly increase error correction thresholds. In this work, we explore the challenges of using a specific tailored code, the XY surface code, for fault-tolerant quantum computation. We introduce efficient and fault-tolerant decoders, belief-matching and belief-find, which exploit correlated hyperedge fault mechanisms present in circuit-level noise. Using belief-matching, we find that the XY surface code has a higher threshold and lower overhead than the square CSS surface code for moderately biased noise. However, the rectangular CSS surface code has a lower qubit overhead than the XY surface code when below threshold. We identify a contributor to the reduced performance that we call fragile boundary errors. These are string-like errors that can occur along spatial or temporal boundaries in planar architectures or during logical state preparation and measurement. While we make partial progress towards mitigating these errors by deforming the boundaries of the XY surface code, our work suggests that fragility could remain a significant obstacle, even for other tailored codes. We expect that our decoders will have other uses; belief-find has an almost-linear running time, and we show that it increases the threshold of the surface code to 0.937(2)% in the presence of circuit-level depolarising noise, compared to 0.817(5)% for the more computationally expensive minimum-weight perfect matching decoder.Comment: 16 pages, 17 figure

Comparison between the implementations of a BCH DVB-S2X decoder in FPGA and in ASIC

Trabalho de conclusão de curso (graduação)—Universidade de Brasília, Faculdade de Tecnologia, Curso de Graduação em Engenharia de Controle e Automação, 2019.Comunicação satelital é uma parte muito importante no sistema de comunicação global, por- tanto padrões que garantam seu funcionamento devem ser aplicados por meio de especificação de comportamentos e algoritmos. Entre esses padrões está o Digital Video Broadcasting - Satellite Second Generation Extended, DVB-S2X, uma evolução do Digital Video Broadcasting - Satellite, DVB-S. Nesse padrão, para corrigir as mensagens recebidas que podem sofrer erros durante a transmissão, são utilizados códigos de correção de erro tais como o Low Density Parity Check, LDPC, e o Bose-Chauduri-Hoquenghem, BCH. A implementação desses algoritmos em um sis- tema digital é realizada através de uma plataforma apropriada. Para isso podem ser utilizados Field Programmable Gate Arrays, FPGAs, ou um sistema Application Specific Integrated Circuit, ASIC. Ao utilizar uma implementação ASIC, ferramentas Electronic Design Automation, EDA, e Computer Aided Design, CAD, são usadas para poder auxiliar o desenvolvimento. Neste trabalho, tomando como ponto de partida uma implementação em FPGA de um decodificador BCH previ- amente realizada, foi feita uma adaptação para fluxo de projeto de ASIC digital e sua validação por simulação com emprego do framework do Cadence Design Systems. Para isso utilizou uma especificação de 100MHz de clock buscando consumo menor do que a implementação da FPGA. Para auxiliar o desenvolvimento foi criado um script em Bash para automatizar a síntese lógica de várias tecnologias e configurações de metais. A comparação de consumo de potência, tem- porização e área foi feita utilizando os resultados da síntese lógica nas tecnologias de 180nm da XFAB. A partir dos dados analisados foi encontrada uma implementação em ASIC com uma fre- quência máxima de clock de 490MHz com um consumo abaixo de 960 mW ocupando uma área de aproximadamente 101 mm2. O modelo em FPGA apresentou uma frequência nominal de 100MHz com um consumo de 620 mW. O modelo em ASIC para a mesma frequência teve um consumo de 175 mW. Comparando os dois modelos conclui-se que uma implementação em ASIC pode levar a ganhos consideravéis no consumo e em desempenho. Para a especificação todas as soluções em ASIC tiveram um consumo menor e todas as tecnologias permitem aumentar o desempenho total do sistema.Satellite communication is a very important part of the global communication system. There- fore, standards that ensure its operation must be applied through the specification of behaviors and algorithms. Among these standards there is the Digital Video Broadcasting - Satellite Second Generation Extended, DVB-S2X, an evolution of the Digital Video Broadcasting - Satellite, DVB- S. Within this standard, to correct the received messages that can suffer errors during transmission, error correction codes such as the Low Density Power Converter, LDPC, and the Bose-Chauduri- Hoquenghem, BCH, are utilized. The implementation of these algorithms in a digital system is performed through an adequate platform. For that, Field Programmable Gate Arrays, FPGAs, can be utilized, or an Application Specific Integrated Circuit, ASIC, can be created. In the ASIC implementation, Eletronic Design Automation, EDA, tools and Computer Aided Design, CAD, are used to facilitate the development. In this work, utilizing a previously made implementation in FPGA of a BCH decoder, an adaptation for the ASIC digital design flow and itsvalidation through simulation with the use of the Cadence Design System framework. The comparison be- tween power consumption, timing and area were made using the results of the logical synthesis in XFAB technologies. From the analysed data, an ASIC implementation with maximum frequency of 490MHz with a power consumption below 960 mW occupying an area of approximately 101 mm2 was found. The FPGA model presented a nominal frequency of 100MHz and power con- sumption of 620 mW. The ASIC model for the same frequency presented power consumption of 175 mW. Comparing these two models, it can be seen that the ASIC implementation can lead to considerable gains in power consumption and performance

Practical Issues in GPRAM Development

In this thesis, two parts of practical issues in the GPRAM system design are included. The first part is the coding part. The sum-product decoding algorithm of LDPC codes has been refined to fit for the GPRAM hardware implementation. As we all know, communication channel has noise. The noise in telecom system is different from that in GPRAM systems. So the noise should be handled well in the GPRAM design. A noise look-up table was created for FPGA and those noises in the table are quantized. The second part of the thesis is to convert perfect images in video stream to those similar to the coarse images in human vision. GPRAM is an animal like robot in which coarse images are needed more than the fine images in order for us to understand how to GPRAM progresses those images to generate as clear image as we experienced. We use three steps, Point Spread function, inserting Poisson Noise, and introducing Eye fixation movements to mimic the coarse images seen merely from our eyes at the retinal photo-receptor level, i.e., without any brain processing

Implementation of reed solomon error correcting codes

In the present world, communication has got many applications such as telephonic conversations etc. in which the messages are encoded into the communication channel and then decoding it at the receiver end. During the transfer of message, the data might get corrupted due to lots of disturbances in the communication channel. So it is necessary for the decoder tool to also have a function of correcting the error that might occur. Reed Solomon codes are type of burst error detecting codes which has got many applications due to its burst error detection and correction nature. My aim of the project is to implement this reed Solomon codes in a VHDL test bench waveform and also to analyse the error probability that is occurring during transmission. To perform this check one can start with simulating reed Solomon codes in MATLAB and then going for simulation in XILINX writing the VHDL code. The encoder and decoder design of reed Solomon codes have got different algorithms. Based on your requirements you can use those algorithms. The difference between the algorithms is that of the computational calculations between them. The complexity of the code depends on the algorithm used. I will be using Linear Feedback Shift Register circuit for designing the encoder