1,545 research outputs found
Low-Power Soft-Error-Robust Embedded SRAM
Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not
damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for the increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes up to 90% of the die in microprocessors and SoCs (System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system.
In this work, a soft-error-robust eight-transistor SRAM cell (8T) is proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transients (SET), the proposed approach is evaluated. For the purpose of analysis and comparisons the results of 8T cell are compared with a standard 6T SRAM cell and the state-of-the-art soft-error-robust
SRAM cells. Based on simulation results in a 65-nm commercial CMOS process, the 8T cell
demonstrates higher immunity to SETs along with smaller area and comparable leakage
power. A 32-kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness.
As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of cancelling the
input offset voltage is presented. The simulated and measured results in 180-nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier, when compared with a conventional sense amplifier, has a similar die area and a greatly reduced offset voltage. Additionally, a dual-input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.1 yea
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Ultra-Low-Power Sensors and Receivers for IoT Applications
The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion
Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies
The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filterโs transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection
Advances in Microelectronics for Implantable Medical Devices
Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of todayโs implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field
A 128Kb RAM Design with Capacitor-Based Offset Compensation and Double-Diode based Read Assist Circuits at Low VDD
Low power static random access memory (SRAM) takes significant portion of area on chip in all modern SOCs and emerging Computing-in-memory applications for edge devices in IoT. This work proposes novel readability assist with the double-diode based word line under drive (WLUD) has been effective improving the read-static noise-margin (RSNM) by 26โ46%and proposed a capacitor based current controlled sense amplifier offset compensation scheme. This scheme achieves 4X reduction in standard deviation of offset voltage over conventional sense amplifier design with 1.1% and 2.9% of area, power overheads respectively with 90 nm CMOS technology at 0.5โ1.0 V supply voltages
A 128Kb RAM Design with Capacitor-Based Offset Compensation and Double-Diode based Read Assist Circuits at Low VDD
788-793Low power static random access memory (SRAM) takes significant portion of area on chip in all modern SOCs and emerging Computing-in-memory applications for edge devices in IoT. This work proposes novel readability assist with the double-diode based word line under drive (WLUD) has been effective improving the read-static noise-margin (RSNM) by 26โ46%and proposed a capacitor based current controlled sense amplifier offset compensation scheme. This scheme achieves 4X reduction in standard deviation of offset voltage over conventional sense amplifier design with 1.1% and 2.9% of area, power overheads respectively with 90 nm CMOS technology at 0.5โ1.0 V supply voltages
์ฐจ์ธ๋ ์๋์ฐจ์ฉ ์นด๋ฉ๋ผ ๋ฐ์ดํฐ ํต์ ์ ์ํ ๋น๋์นญ ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์ ์ค๊ณ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .๋ณธ ํ์ ๋
ผ๋ฌธ์์๋ ์ฐจ์ธ๋ ์๋์ฐจ์ฉ ์นด๋ฉ๋ผ ๋งํฌ๋ฅผ ์ํด ๋์ ์๋์ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ์ ๋ฎ์ ์๋์ 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ๋ฅผ ํต์ ํ๋ ๋น๋์นญ ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์ ์ค๊ณ ๊ธฐ์ ์ ๋ํด ์ ์ํ๊ณ ๊ฒ์ฆ๋์๋ค.
์ฒซ๋ฒ์งธ ํ๋กํ ํ์
์ค๊ณ์์๋, 10B6Q ์ง๋ฅ ๋ฐธ๋ฐ์ค ์ฝ๋๋ฅผ ํ์ฌํ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ก์ ๊ธฐ์ ๊ณ ์ ๋ ๋ฐ์ดํฐ์ ์ฐธ์กฐ ๋ ๋ฒจ์ ๊ฐ์ง๋ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ์ํ ์์ ๊ธฐ์ ๋ํ ๋ด์ฉ์ด ๊ธฐ์ ๋์๋ค. 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ก์ ๊ธฐ์์๋ ๊ต๋ฅ ์ฐ๊ฒฐ ๋งํฌ ์์คํ
์ ๋์ํ๊ธฐ ์ํ ๋ฉด์ ๋ฐ ์ ๋ ฅ ํจ์จ์ฑ์ด ์ข์ 10B6Q ์ฝ๋๊ฐ ์ ์๋์๋ค. ์ด ์ฝ๋๋ ์ง๋ฅ ๋ฐธ๋ฐ์ค๋ฅผ ๋ง์ถ๊ณ ์ฐ์์ ์ผ๋ก ๊ฐ์ ์ฌ๋ณผ์ ๊ฐ์ง๋ ๊ธธ์ด๋ฅผ 6๊ฐ๋ก ์ ํ ์ํจ๋ค. ๋น๋ก ์ฌ๊ธฐ์๋ ์
๋ ฅ ๋ฐ์ดํฐ ๊ธธ์ด 10๋นํธ๋ฅผ ์ฌ์ฉํ์์ง๋ง, ์ ์๋ ๊ธฐ์ ์ ์นด๋ฉ๋ผ์ ๋ค์ํ ๋ฐ์ดํฐ ํ์
์ ๋์ํ ์ ์๋๋ก ์
๋ ฅ ๋ฐ์ดํฐ ๊ธธ์ด์ ๋ํ ํ์ฅ์ฑ์ ๊ฐ์ง๋ค. ๋ฐ๋ฉด, 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ์ํ ์์ ๊ธฐ์์๋, ์ํ๋ฌ์ ์ต์
์ ์ต์ ์ผ๋ก ์ ๊ฑฐํ์ฌ ๋ ๋ฎ์ ๋นํธ์๋ฌ์จ์ ์ป๊ธฐ ์ํด์, ๊ธฐ์กด์ ๋ฐ์ดํฐ ๋ฐ ์ฐธ์กฐ ๋ ๋ฒจ์ ์กฐ์ ํ๋ ๋์ , ์ด ๋ ๋ฒจ๋ค์ ๊ณ ์ ์ํค๊ณ ๊ฐ๋ณ ๊ฒ์ธ ์ฆํญ๊ธฐ๋ฅผ ์ ์ํ์ผ๋ก ์กฐ์ ํ๋๋ก ํ์๋ค. ์๊ธฐ 10B6Q ์ฝ๋ ๋ฐ ๊ณ ์ ๋ฐ์ดํฐ ๋ฐ ์ฐธ์กฐ๋ ๋ฒจ ๊ธฐ์ ์ ๊ฐ์ง ํ๋กํ ํ์
์นฉ๋ค์ 40 ๋๋
ธ๋ฏธํฐ ์ํธ๋ณด์ํ ๋ฉํ ์ฐํ ๋ฐ๋์ฒด ๊ณต์ ์ผ๋ก ์ ์๋์๊ณ ์นฉ ์จ ๋ณด๋ ํํ๋ก ํ๊ฐ๋์๋ค. 10B6Q ์ฝ๋๋ ํฉ์ฑ ๊ฒ์ดํธ ์ซ์๋ 645๊ฐ์ ํจ๊ป ๋จ 0.0009 mm2 ์ ๋ฉด์ ๋ง์ ์ฐจ์งํ๋ค. ๋ํ, 667 MHz ๋์ ์ฃผํ์์์ ๋จ 0.23 mW ์ ์ ๋ ฅ์ ์๋ชจํ๋ค. 10B6Q ์ฝ๋๋ฅผ ํ์ฌํ ์ก์ ๊ธฐ์์ 8-Gb/s 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ๋ฅผ ๊ณ ์ ๋ฐ์ดํฐ ๋ฐ ์ฐธ์กฐ ๋ ๋ฒจ์ ๊ฐ์ง๋ ์ ์ํ ์์ ๊ธฐ๋ก 12-m ์ผ์ด๋ธ (22-dB ์ฑ๋ ๋ก์ค) ์ ํตํด์ ๋ณด๋ธ ๊ฒฐ๊ณผ ์ต์ ๋นํธ ์๋ฌ์จ 108 ์ ๋ฌ์ฑํ์๊ณ , ๋นํธ ์๋ฌ์จ 105 ์์๋ ์์ด ๋ง์ง์ด 0.15 UI x 50 mV ๋ณด๋ค ํฌ๊ฒ ์ธก์ ๋์๋ค. ์ก์์ ๊ธฐ๋ฅผ ํฉ์น ์ ๋ ฅ ์๋ชจ๋ 65.2 mW (PLL ์ ์ธ) ์ด๊ณ , ์ฑ๊ณผ์ ๋ํ์์น๋ 0.37 pJ/b/dB ๋ฅผ ๋ณด์ฌ์ฃผ์๋ค.
์ฒซ๋ฒ์งธ ํ๋กํ ํ์
์ค๊ณ์ ํฌํจํ์ฌ ๊ฐ์ ๋ ๋๋ฒ์งธ ํ๋กํ ํ์
์ค๊ณ์์๋, 12-Gb/s 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ๋ฐฉํฅ ์ฑ๋ ์ ํธ์ 125-Mb/s 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ญ๋ฐฉํฅ ์ฑ๋ ์ ํธ๋ฅผ ํ์ฌํ ๋น๋์นญ ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์ ๋ํด ๊ธฐ์ ๋๊ณ ๊ฒ์ฆ๋์๋ค. ์ ์๋ ๋์ ์ ํ ๋ฒ์๋ฅผ ๊ฐ์ง๋ ํ์ด๋ธ๋ฆฌ๋๋ gmC ์ ๋์ญ ํต๊ณผ ํํฐ์ ์์ฝ ์ ๊ฑฐ๊ธฐ์ ํจ๊ป ์์๋ฐ์ด๋ ์ ํธ๋ฅผ 24 dB ์ด์ ํจ์จ์ ์ผ๋ก ๊ฐ์์์ผฐ๋ค. ๋ํ, ๋์ ์ ํ ๋ฒ์๋ฅผ ๊ฐ์ง๋ ํ์ด๋ธ๋ฆฌ๋์ ํจ๊ป ๊ฒ์ธ ๊ฐ์๊ธฐ๋ฅผ ํ์ฑํ๊ฒ ๋๋ ์ ํ ๋ฒ์ ์ฆํญ๊ธฐ๋ฅผ ํตํด 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ์ ์ ํ์ฑ๊ณผ ์งํญ์ ํธ๋ ์ด๋ ์คํ ๊ด๊ณ๋ฅผ ๊นจ๋ ๊ฒ์ด ๊ฐ๋ฅํ์๋ค. ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ ์นฉ์ 40 ๋๋
ธ๋ฏธํฐ ์ํธ๋ณด์ํ ๋ฉํ ์ฐํ ๋ฐ๋์ฒด ๊ณต์ ์ผ๋ก ์ ์๋์๋ค. ์๊ธฐ ์ค๊ณ ๊ธฐ์ ๋ค์ ์ด์ฉํ์ฌ, 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ๋ฐ 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ก์์ ๊ธฐ ๋ชจ๋ 5m ์ฑ๋ (์ฑ๋ ๋ก์ค 15.9 dB) ์์ 1E-12 ๋ณด๋ค ๋ฎ์ ๋นํธ ์๋ฌ์จ์ ๋ฌ์ฑํ์๊ณ , ์ด 78.4 mW ์ ์ ๋ ฅ ์๋ชจ๋ฅผ ๊ธฐ๋กํ์๋ค. ์ข
ํฉ์ ์ธ ์ก์์ ๊ธฐ๋ ์ฑ๊ณผ ๋ํ์งํ๋ก 0.41 pJ/b/dB ์ ํจ๊ป ๋์ ์๋ฐฉํฅ ํต์ ์๋์์ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ ๋ฐ 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ ๊ฐ๊ฐ์์ ์์ด ๋ง์ง 0.15 UI ์ 0.57 UI ๋ฅผ ๋ฌ์ฑํ์๋ค. ์ด ์์น๋ ์ฑ๊ณผ ๋ํ์งํ 0.5 ์ดํ๋ฅผ ๊ฐ์ง๋ ๊ธฐ์กด ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์์ ๋น๊ต์์ ์ต๊ณ ์ ์์ด ๋ง์ง์ ๊ธฐ๋กํ์๋ค.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link.
In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB.
In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 DISSERTATION ORGANIZATION 4
CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6
2.1 OVERVIEW 6
2.2 SYSTEM REQUIREMENTS 10
2.2.1 CHANNEL 10
2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12
2.2.3 AC COUPLING AND DC BALANCE CODE 15
2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18
2.2.4.1 HYBRID 18
2.2.4.2 ECHO CANCELLER 20
2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22
CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25
3.1 INTRODUCTION 25
3.2 PRIOR WORKS 28
3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30
3.4 DESIGN OF THE 10B6Q CODE 33
3.4.1 PAM-4 DC BALANCE 35
3.4.2 PAM-4 TRANSITION DENSITY 35
3.4.3 10B6Q DECODER 37
3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40
CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45
4.1 INTRODUCTION 45
4.2 PRIOR WORKS 47
4.3 ARCHITECTURE AND IMPLEMENTATION 49
4.2.1 PAM-4 TRANSMITTER 49
4.2.2 PAM-4 ADAPTIVE RECEIVER 52
4.3 MEASUREMENT RESULTS 62
CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68
5.1 INTRODUCTION 68
5.2 PRIOR WORKS 70
5.3 WIDE LINEAR RANGE (WLR) HYBRID 75
5.3 IMPLEMENTATION 78
5.3.1 SERIALIZER (SER) DESIGN 78
5.3.2 DESERIALIZER (DES) DESIGN 79
5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82
5.5 MEASUREMENT RESULTS 88
CHAPTER 6 CONCLUSION 97
BIBLIOGRAPHY 99
์ด ๋ก 106๋ฐ
A new offset cancellation technique for temperature sensors & Design of 8-bit decimation filter for biomedical applications
In our day to day life there are lot of things which we need to sense and then decide the course of action according to it. Many of these can be physically sensed easily, but the exact value of the sensed cannot be determined by human. There will be a lot of error in judged value and exact value. So instead of human sensing them and judging the exact value there are physical instruments which can provide lot more accurate value of sensed item than human, which are called SENSORS.
There are lot of different sensors for sensing different things and one of prominent one is temperature sensor. Temperature sensor plays an important role in many applications. For example, maintaining a specific temperature is essential for equipment used to fabricate medical drugs, heat liquids or clean other equipment. For application like these, the accuracy of detection can be critical.
The work done in this Thesis shows how to maintain the accuracy of temperature sensor. Temperature sensor used here is a Wheatstone bridge circuit consisting of two resistors and two thermistors. Mismatch between the resistors or thermistors will lead to incorrect detection of value, which is called OFFSET, therefore to maintain the accuracy the mismatch has to be minimized or removed. One of the Technique to minimize the offset and results pertaining to it has been displayed in this Thesis.
Technique described in this Thesis consist of first sensing the difference between resistors value, one being the reference resistor and other the on-chip resistor used in temperature sensing, second amplifying the difference of resistor value using OPAMP, third sending the amplified signal to single ended SAR ADC, which gives digital bits as output. And according to the digital output changing resistor value using resistor switching method. Thus then this resistor will be used in wheat stone bridge temperature sensing.
The work proposed here can increase or decrease on-chip resistor value depending on reference resistor. The wheat stone bridge Resistor can be changed by plus minus 5K ohms with respect to reference resistor.
This is a onetime calibration technique used before start of sensing temperature. After the resistor have been calibrated, these resistors are used in wheat stone bridge along with thermistor to sense temperature and the differential output obtained through wheat stone is
passed on to the dual ended SAR ADC, which gives digital representation of temperature sensed
Development of the Carbon Nanotube Thermoacoustic Loudspeaker
Traditional speakers make sound by attaching a coil to a cone and moving that coil back and forth in a magnetic field (aka moving coil loudspeakers). The physics behind how to generate sound via this velocity boundary condition has largely been unchanged for over a hundred years. Interestingly, around the time moving coil loudspeakers were first investigated the idea of using heat to generate sound was also known. These thermoacoustic speakers heat and cool a thin material at acoustic frequencies to generate the pressure wave (i.e. they use a thermal boundary condition). Unfortunately, when the thermoacoustic principle was initially discovered there was no material with the right properties to heat and cool fast enough. Carbon nanotube (CNT) loudspeakers first generated sound early in the 21st century. At that time there were many questions unanswered about their place in the sound generation toolbox of an engineer.
The main goal of this dissertation was to continue the development of the CNT loudspeaker with focus on practical usage for an acoustic engineer. Prior to 2014, when this effort began, most of the published development work was from material scientists with objective acoustic performance data presented that was not useful beyond the scope of that particular publication. For example, low sound pressure levels in the nearfield at low power inputs was a common metric. Therefore, this effort had three main objectives with emphasis placed on acquiring data at levels and in nomenclature that would be useful to acoustic engineers so they could bring the technology to market, if adequate.
Investigation into the true power efficiency of CNT loudspeakers
Investigation into alternative methods to linearize the pressure response of
CNT loudspeakers
Investigation into the sound quality of CNT loudspeakers
Overall, it was found that CNT loudspeakers are approximately four orders of magnitude less power efficient than traditional moving coil loudspeakers. The non-linear pressure output of the CNT loudspeakers can be linearized with a variety of drive signal processing methods, but the selection of which method to use depends on a variety of factors (e.g. amplification architecture available). In general, all methods studied are on the same order of magnitude power efficiency, but the direct current offset and amplitude modulation drive signal processing methods are superior in terms of sound quality
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