Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication

Kecerdasan matematik-logik dalam kalangan pelajar sarjana Pendidikan Teknik dan Vokasional UTHM

Kecerdasan matematik-logik sering dikaitkan dengan penguasaan pelajar dalam subjek matematik. Pencapaian pelajar, khususnya pelajar Sarjana Pendidikan Teknik dan Vokasional, Universiti Tun Hussein Onn Malaysia (UTHM) dalam kursus Statistik dalam Penyelidikan sedikit sebanyak mempengaruhi pencapaian akademik pelajar. Oleh itu, kajian ini dijalankan untuk mengkaji pengaruh kecerdasan matematik-logik terhadap pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Kajian berbentuk tinjauan secara kuantitatif untuk melihat hubungan diantara dua pembolehubah iaitu pembolehubah tidak bersandar (kecerdasan matematik-logik) dan pembolehubah bersandar (penguasaan pelajar dalam kursus Statistik dalam Penyelidikan). Persampelan rawak mudah digunakan dalam kajian ini dengan mengambil sampel seramai 108 orang pelajar Sarjana Pendidikan Teknik dan Vokasional sebagai responden kajian. Data diperoleh daripada sampel dengan menggunakan borang soal selidik yang diolah berdasarkan alat pengukuran kecerdasan MIDAS (Multiple Intelligence Development Assessment Scales). Data dianalisis menggunakan perisian SPSS (Statistical Package for Social Science) versi 16.0 yang melibatkan ujian statistik skor min dan kolerasi pangkat Spearman. Hasil dapatan kajian menunjukkan tahap kecenderungan kecerdasan matematik-logik pelajar berada pada tahap yang tinggi dan mempunyai hubungan yang signifikan dengan pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Berdasarkan dapatan kajian boleh disimpulkan bahawa kecerdasan matematik-logik dapat dijadikan kayu ukur dalam memastikan kejayaan pelajar

Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators

Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem. The integration of the ARM processor enables to exploit the possibility of embedded Linux features for high system flexibility. As a result, the proposed ECC accelerator requires limited area, with only 3395 LUTs on the Zynq device used to perform high-speed, 233-bit ECSMs in 413 µs, with a 50 MHz clock. Moreover, the generation of a 384-bit TLS handshake secret key between client and server coordinators requires 67.5 ms on a low cost Zynq 7Z007S device

Constructing cluster of simple FPGA boards for cryptologic computations

In this paper, we propose an FPGA cluster infrastructure, which can be utilized in implementing cryptanalytic attacks and accelerating cryptographic operations. The cluster can be formed using simple and inexpensive, off-the-shelf FPGA boards featuring an FPGA device, local storage, CPLD, and network connection. Forming the cluster is simple and no effort for the hardware development is needed except for the hardware design for the actual computation. Using a softcore processor on FPGA, we are able to configure FPGA devices dynamically and change their configuration on the fly from a remote computer. The softcore on FPGA can execute relatively complicated programs for mundane tasks unworthy of FPGA resources. Finally, we propose and implement a fast and efficient dynamic configuration switch technique that is shown to be useful especially in cryptanalytic applications. Our infrastructure provides a cost-effective alternative for formerly proposed cryptanalytic engines based on FPGA devices