Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Wafer-level processing of ultralow-loss Si3N4

Photonic integrated circuits (PICs) are devices fabricated on a planar wafer that allow light generation, processing, and detection. Photonic integration brings important advantages for scaling up the complexity and functionality of photonic systems and facilitates their mass deployment in areas where large volumes and compact solutions are needed, e.g., optical interconnects. Among the material platforms available, silicon nitride (Si3N4) displays excellent optical properties such as broadband transparency, moderately high refractive index, and relatively strong nonlinearities. Indeed, Si3N4 integrated waveguides display ultralow-loss (few decibels per meter), which enables efficient light processing and nonlinear optics. Moreover, Si3N4 is compatible with standard complementary metal oxide semiconductor (CMOS) processing techniques,which facilitates the manufacture scalability required by mass deployment of PICs. However, the selection of a single photonic platform sets limitations to the device functionalities due to the intrinsic properties of the material and the fundamental limitation of optical waveguiding. Multilayer integration of different platforms can overcome the limitations encountered in a singleplatform PIC.This thesis presents the development of advanced techniques for the waferlevel manufacturing of ultralow-loss Si3N4 devices and approaches to enable their interface with active components like modulators and chip-scale comb sources (microcombs). The investigation covers the tailoring of a waveguide to the functionality required, the wafer-scale manufacturing of Si3N4, and how to overcome the limitations of a single platform on a wafer. These studies enable high-yield fabrication of microcombs, the integration of two Si3N4 platforms on the same wafer, and a strategy to efficiently couple to an integrated LiNbO3 layer to expand the chip functionality and scale up the complexity of the PIC

トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.北九州市立大

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved

Optical Waveguide End Facet Roughness and Optical Coupling Loss

This paper investigates the end facet roughness of multimode polymer channel waveguides fabricated on FR4 printed circuit boards, PCBs, when cut at right angles to their optical axis by milling routers for optical butt-coupling connectors and compares it with that resulting from dicing saws and polishing and proposes a novel end facet treatment. RMS surface roughness of waveguide end facets, measured by AFMs, are compared for a range of rotation speeds and translation speeds of a milling router. It was found that one-flute routers gave significantly less rough surfaces than two or three-flute routers. The best results were achieved for a one-flute router when the milling bit was inserted from the PCB side of the board with a rotation speed of 15,000 rpm and a translation speed of 0.25 m/min which minimized the waveguide core end facet RMS roughness to 183 ± 13 nm and gave input optical coupling loss of 1.7 dB ± 0.5 B and output optical coupling loss of 2.0 dB ± 0.7 dB. The lowest RMS roughness was obtained at chip loads of 16 μm/revolution. High rotation speeds should be avoided as smearing of the end facet occurs possibly due to polymer heating and softening. For the first time to our knowledge, channel waveguide optical insertion loss is shown to be linearly proportional to the ratio of the waveguide core end facet RMS roughness to its autocorrelation length. A new fabrication technique for cut waveguide end facet treatment is proposed and demonstrated which reduces the insertion loss by 2.60 dB ± 1.3 dB which is more than that achieved by the closest available index matching fluid which gave 2.23 dB ± 1.2 dB. The new fabrication method gives a more robust end facet for use in commercial products