Implémentation, ajustement laser et modélisation des convertisseurs numériques à analogique R2R

La conversion numérique à analogique -- Principales caractéristiques des CNA -- Algorithmes et architectures de conversion -- Techniques de linéarisation -- Le CNA R2R inversé -- Un CNA 14 bits ajusté au laser et fabriqué dans une technologie CMOS standard -- Puce -- Montage de test -- Notes et résultats de tests -- Une compensation améliorée pour les interrupteurs des CNA R2R inversés -- Modélisation des CNA R2R

A 0.29 MM2 12-BIT SEGMENTED CURRENT STEERING DAC WITH DIGITALLY ASSISTED ERROR COMPENSATION GROUPING

Ph.DDOCTOR OF PHILOSOPH

Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance

A time-based energy-efficient analog-to-digital converter

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 123-129).Dual-slope converters use time to perform analog-to-digital conversion but require 2N+1 clock cycles to achieve N bits of precision. We describe a novel algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive sub-ranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating Voltage-to-Time and Time-to-Voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an effcient mechanism for amplification and error cancellation allow for energy-effcient operation: In a 0.35 [mu]m implementation, we were able to achieve 12 bits of DNL limited precision or 11 bits of thermal noise-limited precision at a sampling frequency of 31.25kHz with 75 [mu] W of total analog and digital power consumption. These numbers yield a thermal noise-limited energy-efficiency of 1.17pJ per quantization level making it one of the most energy-effcient converters to date in the 10 to 12 bit precision range.(cont.) This converter could be useful in low-power hearing aids after analog gain control has been performed on a microphone front-end. An 8 bit audio version of our converter in a 0.18 [mu] m process consumes 960nW and yields an energy-efficiency of 0.12pJ per quantization level, perhaps the lowest ever reported. This converter may be useful in biomedical and sensor-network applications where energy-efficiency is paramount. Our algorithm has inherent advantages in time-to-digital conversion. It can be generalized to easily digitize power-law functions of its input, and it can be used in an interleaved architecture if higher speed is desired.by Heemin Yi Yang.Ph.D

A multi-bit hybrid DSM over full-scale range without feedback DEM

Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a ∆Σ ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) ∆Σ Modulator (∆ΣM) is inadequate for low-power wideband applications due to the opamp settling requirement. Alternatively, a continuous-time (CT) ∆ΣM can be used to decrease power consumption but has its own disadvantages such as clock jitter sensitivity, RC time constant variation, and excess loop delay. The wideband modulators are often implemented as single-loop high-order modulators in a deep submicron process. The high-order modulator typically has a quantizer overloading problem as the input signal approaches to a full-scale range. A pole-optimization method can be used to extend the linear input range but it inevitably decreases signal to quantization noise ratio. This causes power penalty since it limits the maximum input power available. Another challenge is linearizing a nonlinear multi-bit Digital-to-Analog Converter (DAC). On one hand, the DAC can be linearized by element sizing, sorting, and calibration but these increase silicon area and power consumption. On the other hand, a Dynamic Element Matching algorithm (DEM) linearizes the DAC by averaging and shaping the mismatches with minimal design overhead. However, the DEM causes additional delay inside the feedback path. This can make the modulator unstable. In this thesis, a multi-bit 3rd-order hybrid ∆ΣM with over full-scale range and no DEM in the critical feedback path is presented. Removing the DEM in the critical path enables the modulator to minimize latency in the feedback path. A digital feedforward structure allows processing the input signal over the full-scale reference voltage. Combined benefits of the CT/DT implementation help to reduce power consumption and to mitigate the loop delay. Measurement results from a prototype demonstrate the effectiveness of the proposed ideas

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Bandpass electromechanical sigma-delta modulator

Ph.DDOCTOR OF PHILOSOPH

Contribution à l’étude et la réalisation d’un générateur de signaux radiofréquences analogiques pour la radio logicielle intégrale

The increasing density of wireless devices and the associated communication flows sharing the same air interface will require a smart and agile use of frequency resources. This thesis proposes a flexible, low cost and low power disruptive transmitter architecture. It uses a differentiating coding scheme which leverages a mathematical and technological reduction of the energy cost of information conversion. The design of a DAC suited to this architecture is developed and its performances are assessed toward RF signal generation. The measurements of a demonstrator designed in 65 nm CMOS technology bring a proof of concept.Une utilisation intelligente de l’espace Hertzien sera nécessaire pour permettre au nombre croissant d’objets sans-fil connectés de communiquer dans le même espace de propagation. Ces travaux de thèse proposent une architecture d’émetteur radiofréquence flexible, faible coût et faible consommation, en rupture avec les techniques conventionnelles. Cet émetteur est fondé sur un encodage de la dérivée du signal à générer, ce qui permet de réduire le coût énergétique de la conversion de l’information. Un convertisseur numérique analogique compatible avec cette architecture est présenté et ses performances sont évaluées dans le cadre de la génération de signaux radiofréquence. Les résultats de mesures obtenus avec un prototype réalisé en technologie CMOS 65 nm apporte la preuve du concept