A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications

Clocking is an important aspect of digital VLSI system design. The design of high-performance and low-power clocked storage elements is essential and critical to achieving maximum levels of performance and reliability in modern VLSI systems such as Systems on Chips (SoCs). In this thesis, a pulse-clocked double edge-triggered D-flip-flop (PDET) is proposed. PDET uses a new split-output true single-phase clocked (TSPC) latch and when clocked by a short pulse train acts like a double edge-triggered flip-flop. The P-type version of the new TSPC split-output latch is compared with existing TSPC split-output latches in terms of robustness, area, and power efficiency at high-speeds. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches. The novel double edge-triggered flip-flop uses only eight transistors with only one N-type transistor being clocked. Compared to other double edge-triggered flip-flops, PDET offers advantages in terms of speed, power, and area. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Period-Power product is reduced by 56%-63% compared to other double edge-triggered flip-flops. Simulations are performed using HSPICE in CMOS 0.5 om technology. This design is suitable for high-speed, low-power CMOS VLSI design applications

Individual flip-flops with gated clocks for low power datapaths

Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.Peer ReviewedPostprint (published version

A New Area and Power Efficient Single Edge Triggered Flip-Flop Structure for Low Data Activity and High Frequency Applications

In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The proposed design is compared with six existing flip-flop designs. In the proposed design, the number of transistors is reduced to decrease the area. The number of clocked transistors of the devised flip-flop is also reduced to minimize the power consumption. As compared to the other state of the art single edge triggered flip-flop designs, the newly proposed design is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption. The proposed flip-flop also has the lowest transistor count and the lowest area. The simulation results show that the proposed flip-flop is best suited for low power and low area systems especially for low data activity and high frequency applications. Keywords: PDP, reliability, delay, process node, clock frequenc

Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology

Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor

In VLSI system design, power consumption is the ambitious issue for the past respective years. Advanced IC fabrication technology grants the use of nano scaled devices, so the power dissipation becomes major problem in the designing of VLSI chips. In this paper we present, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme using pass transistor. The offered design successfully figure out the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better power performance by consuming low power. The proposed design also significantly reduces delay time, set-up time and hold time. Simulation results based on TMC 180nm CMOS technology reveal that the proposed design features the best power and delay performance in several FF designs under comparison

Single Edge Triggered Static D Flip-Flops: Performance Comparison

Due to fast growth of portable devices, power consumption and timing delays are the two important design parameters in high speed and low power VLSI design arena. In this paper we presents the comparison of single edge triggered static D flip-flop designs to show the benefit of power consumption ,delay and power delay product on the basis of area efficiency. Keywords: Single edge triggered flip-flops, super-threshold region, parasitic capacitance, transmission gat

Novel Low Power and Low Transistor Count Flip-Flop Design with High Performance

The paper proposed a new design of static SET flip-flop for low power applications. In this work, comparative analysis of existing architecture for flip-flops along with the proposed design is made. The comparison is done on the basis of power and power delay product, transistor count is also included. Due to continuous increase in integration of transistors and growing needs of portable equipments, low power design is of prime importance. The proposed design has the best power and the second best PDP than the existing architectures. Proposed FF has the least transistor count hence reducing the manufacturing cost and area. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that for all supply voltages, proposed FF has the best power consumption, second best PDP and the lowest transistor count. So this design is best suited for low power and high performance portable applications. Keywords: Transmission Gate, Short circuit current, Edge Triggered, Optimizatio