An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

Built-In Self-Test Solution for CMOS MEMS Sensors

This thesis presents a new readout circuit with integrated Built-in Self-Test (BIST) structure for capacitive Micro-Electro-Mechanical Systems (MEMS). In the proposed solution instead of commonly used voltage control signals to test the device, charge control stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of MEMS structural collapse in the test phase. Measurement results using a prototype fabricated in TSMC 65nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance

Τεχνικές ελέγχου ορθής λειτουργίας και διόρθωσης επιδόσεων τηλεπικοινωνιακών ολοκληρωμένων κυκλωμάτων υψηλών συχνοτήτων

Στη διατριβή αυτή παρουσιάζονται τεχνικές ελέγχου ορθής λειτουργίας και διόρθωσης επιδόσεων κατάλληλες για αναλογικά ολοκληρωμένα κυκλώματα RF. Ειδικότερα, προτείνεται η ενοποίηση των διαδικασιών ελέγχου ορθής λειτουργίας και διόρθωσης των επιδόσεων ενός κυκλώματος με την αξιοποίηση ενός συνόλου βέλτιστα επιλεγμένων παρατηρήσιμων μεγεθών. Η επεξεργασία των μεγεθών αυτών καθιστά δυνατή, αφενός, την ανίχνευση ελαττωμάτων και, αφετέρου, την πρόγνωση των επιδόσεων του κυκλώματος η οποία επιτρέπει την εξέταση της συμμόρφωσής του προς τις προδιαγραφές, καθώς και τη διόρθωση της συμπεριφοράς του. Προκειμένου να αντιμετωπισθεί το πρόβλημα της προσβασιμότητας στα παρατηρήσιμα μεγέθη προτείνεται ενσωματωμένη τεχνική μέτρησής τους, ενώ αναπτύσσεται μέθοδος για την ελαχιστοποίηση της αβεβαιότητας που υπεισέρχεται στο ίδιο το σύστημα μέτρησης. Εφαρμόζονται, επίσης, αλγόριθμοι επιλογής με σκοπό την μείωση του αριθμού των παρατηρήσιμων μεγεθών, μέσω μιας διαδικασίας βελτιστοποίησης η οποία οδηγεί στη μείωση του κόστους ελέγχου ορθής λειτουργίας με τον περιορισμό της πολυπλοκότητας και της χρονικής διάρκειας διεξαγωγής του. Η αποδοτικότητα των προτεινόμενων τεχνικών επιβεβαιώνεται με την εφαρμογή τους σε τυπικό μίκτη RF τεχνολογίας 0.18μm CMOS, από τον οποίο λαμβάνονται αποτελέσματα προσομοιώσεων που αξιολογούνται και συγκρίνονται με αντίστοιχες συμβατικές τεχνικές.Testing and performance calibration techniques suitable for integrated RF circuits are presented in this dissertation. Specifically, a common approach is proposed for the testing and calibration procedures, that exploits a set of optimally selected observables. The processing of these observables enables defect detection, and also the prediction of the circuit’s performance which allows the examination of compliance with the specifications and performance calibration, as well. In order to address the problem of accessibility to test observables, a built-in technique is proposed, while a method to minimize the uncertainty introduced in the measurement system itself is also described. The application of selection algorithms is explored, aiming to reduce the number of test observables through an optimization procedure that leads to test cost savings due to the reduction of the test conduction complexity and time. The efficiency of the proposed techniques is validated by their application to a typical RF mixer designed in a 0.18um CMOS technology. Simulation results are obtained and assessed, while comparison with similar conventional techniques is also provided