Investigation into the wafer-scale integration of fine-grain parallel processing computer systems

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis investigates the potential of wafer-scale integration (WSI) for the implementation of low-cost fine-grain parallel processing computer systems. As WSI is a relatively new subject, there was little work on which to base investigations. Indeed, most WSI architectures existed only as untried and sometimes vague proposals. Accordingly, the research strategy approached this problem by identifying a representative WSI structure and architecture on which to base investigations. An analysis of architectural proposals identified associative memory to be general purpose parallel processing component used in a wide range of WSI architectures. Furthermore, this analysis provided a set of WSI-level design requirements to evaluate the sustainability of different architectures as research vehicles. The WSI-ASP (WASP) device, which has a large associative memory as its main component is shown to meet these requirements and hence was chosen as the research vehicle. Consequently, this thesis addresses WSI potential through an in-depth investigation into the feasibility of implementing a large associative memory for the WASP device that meets the demanding technological constraints of WSI. Overall, the thesis concludes that WSI offers significant potential for the implementation of low-cost fine-grain parallel processing computer systems. However, due to the dual constraints of thermal management and the area required for the power distribution network, power density is a major design constraint in WSI. Indeed, it is shown that WSI power densities need to be an order of magnitude lower than VLSI power densities. The thesis demonstrates that for associative memories at least, VLSI designs are unsuited to implementation in WSI. Rather, it is shown that WSI circuits must be closely matched to the operational environment to assure suitable power densities. These circuits are significantly larger than their VLSI equivalents. Nonetheless, the thesis demonstrates that by concentrating on the most power intensive circuits, it is possible to achieve acceptable power densities with only a modest increase in area overheads.SER

Self-organising techniques for tolerating faults in 2-dimensional processor arrays

This thesis is concerned with research into techniques for tolerating the defects which inevitably occur in integrated circuits during processing. The research is motivated by the desire to permit the fabrication of very large (> 1cm²) integrated circuits having a viable yield, using standard chip processing lines. Attention is focussed on 2-dimensional arrays of identical processing elements with nearest-neighbour, orthogonal interconnections, and techniques for configuring such arrays in the presence of faults are investigated. In particular, novel algorithms based on the concept of self-organisation are proposed and studied in detail. The algorithms involve associating a small amount of control logic with each processing element in the array. The extra logic allows the processing elements to communicate with each other and come to a collective decision about how working processors should best be interconnected. The concept has been studied in considerable depth and the implications of the algorithms in a practical system have been thoroughly considered and demonstrated by construction of a small array at printed circuit board level, complete with software controlled testing procedures. The thesis can be considered in four main parts as follows. The first part (chapters 1 to 4) starts by presenting the objectives of the research and then motivates it by examining the increasing need for processor arrays. The difficulty of implementing such arrays as monolithic circuits due to integrated circuit defects is then considered. This is followed by a review of published work on hardware fault tolerance for regular arrays of processors. The second part (chapters 5 and 6) is devoted to the concept of self-organisation in processor arrays and includes a detailed description and evaluation of the algorithms followed by a comparison with other published techniques. Considerations such as hardware requirements and overheads, reducing the vulnerability of critical circuitry, self-testing, and the construction of the demonstrator are covered in the third part (chapters 7 to 10). The fourth part (chapters 11 and 12) considers potential applications for the research in both monolithic and non-monolithic systems. Finally, the conclusions and some suggestions for further work are presented

Proceedings of the Caltech Conference on Very Large Scale Integration, held at the California Institute of Technology 22 - 24 January 1979 ; Organized by the Caltech Computer Science Department and the Caltech Industrial Associates Office

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Synthèse de réseaux de distribution d'horloges en présence de variations du procédé de fabrication

Design of clock distributions networks in presence of process variations -- Importance des variations spatiales de la constante de temps du transistor MOS -- Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations -- Conception de réseaux de distribution d'horloges fiables et à faible consommation de puissance -- Design of low-power and reliable logic-based H-trees -- Sources des variations spatiales de la constante de temps du transistor MOS -- Spatial characterization of process variations via MOS transistor time constants in VLSI & WSI -- Techniques de minimisation du biais de synchronisation par calibration de délai -- Minimizing process-induced skew using delay tuning