Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Modeling and experimental verification of single event upsets

The research performed and the results obtained at the Laboratory for Radiation Studies, Prairie View A&M University and Texas A&I University, on the problem of Single Events Upsets, the various schemes employed to limit them and the effects they have on the reliability and fault tolerance at the systems level, such as robotic systems are reviewed

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

The effects of ionising radiation on implantable MOS electronic devices

Space exploration and the rapid growth of the satellite communications industry has promoted substantial research into the effects of ionising radiation on modem electronic technology. The enabling electronics and computer processing has seen a commensurate growth in the use of radiation for diagnostic and therapeutic purposes in medicine. Numerous studies exist in both these fields but an analysis combining the fields of study to ascertain the effects of radiation on medically implantable electronics is lacking. A review of significant ground level radiation sources is presented with particular emphasis on the medical environment. Mechanisms of permanent and transient ionising radiation damage to Metal Oxide Semiconductors are summarised. Three significant sources of radiation are classified as having the ability to damage or alter the behavior of implantable electronics; Secondary neutron cosmic radiation, alpha particle radiation from the device packaging and therapeutic doses of high energy radiation. With respect to cosmic radiation, the most sensitive circuit structure within a typical microcomputer architecture is the Random Access Memory(RAM). A theoretical model which predicts the susceptibility of a RAM cell to single event upsets from secondary cosmic ray neutrons is presented. A previously unreported method for calculating the collection efficiency term in the upset model has been derived along with an extension of the model to enable estimation of multiple bit upset rates. An Implantable Cardioverter Defibrillator is used as a case example to demonstrate model applicability and test against clinical experience. The model correlates well with clinical experience and is consistent with the expected geographical variations of the secondary cosmic ray neutron flux. This is the first clinical data set obtained indicating the effects of cosmic radiation on implantable devices. Importantly, it may be used to predict the susceptibility of future implantable device designs to cosmic radiation. The model is also used as a basis for developing radiation hardened circuit techniques and system design. A review of methods to radiation harden electronics to single event upsets is used to recommend methods applicable to the low power/small area constraints of implantable systems

Index to 1986 NASA Tech Briefs, volume 11, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1986 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Solid State Radiation Dosimeters for Space and Medical Applications

This report describes the development of two radiation monitors (RADMON's) for use in detecting total radiation dose and high-energy particles. These radiation detectors are chip-size devices fabricated in 1.2 micrometer CMOS and have flown in space on both experimental and commercial spacecraft. They have been used to characterize protons and electrons in the Earth's radiation belts, particles from the Sun, and protons used for medical therapy. Having proven useful in a variety of applications, the detector is now being readied for commercialization

Techniques for Aging, Soft Errors and Temperature to Increase the Reliability of Embedded On-Chip Systems

This thesis investigates the challenge of providing an abstracted, yet sufficiently accurate reliability estimation for embedded on-chip systems. In addition, it also proposes new techniques to increase the reliability of register files within processors against aging effects and soft errors. It also introduces a novel thermal measurement setup that perspicuously captures the infrared images of modern multi-core processors