An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step

Accelerated Successive Approximation Technique for Analog to Digital Converter Design

This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation

Compressive Sensing and Multichannel Spike Detection for Neuro-Recording Systems

RÉSUMÉ Les interfaces cerveau-machines (ICM) sont de plus en plus importantes dans la recherche biomédicale et ses applications, tels que les tests et analyses médicaux en laboratoire, la cérébrologie et le traitement des dysfonctions neuromusculaires. Les ICM en général et les dispositifs d'enregistrement neuronaux, en particulier, dépendent fortement des méthodes de traitement de signaux utilisées pour fournir aux utilisateurs des renseignements sur l’état de diverses fonctions du cerveau. Les dispositifs d'enregistrement neuronaux courants intègrent de nombreux canaux parallèles produisant ainsi une énorme quantité de données. Celles-ci sont difficiles à transmettre, peuvent manquer une information précieuse des signaux enregistrés et limitent la capacité de traitement sur puce. Une amélioration de fonctions de traitement du signal est nécessaire pour s’assurer que les dispositifs d'enregistrements neuronaux peuvent faire face à l'augmentation rapide des exigences de taille de données et de précision requise de traitement. Cette thèse regroupe deux approches principales de traitement du signal - la compression et la réduction de données - pour les dispositifs d'enregistrement neuronaux. Tout d'abord, l’échantillonnage comprimé (AC) pour la compression du signal neuronal a été utilisé. Ceci implique l’usage d’une matrice de mesure déterministe basée sur un partitionnement selon le minimum de la distance Euclidienne ou celle de la distance de Manhattan (MDC). Nous avons comprimé les signaux neuronaux clairsemmés (Sparse) et non-clairsemmés et les avons reconstruit avec une marge d'erreur minimale en utilisant la matrice MDC construite plutôt. La réduction de données provenant de signaux neuronaux requiert la détection et le classement de potentiels d’actions (PA, ou spikes) lesquelles étaient réalisées en se servant de la méthode d’appariement de formes (templates) avec l'inférence bayésienne (Bayesian inference based template matching - BBTM). Par comparaison avec les méthodes fondées sur l'amplitude, sur le niveau d’énergie ou sur l’appariement de formes, la BBTM a une haute précision de détection, en particulier pour les signaux à faible rapport signal-bruit et peut séparer les potentiels d’actions reçus à partir des différents neurones et qui chevauchent. Ainsi, la BBTM peut automatiquement produire les appariements de formes nécessaires avec une complexité de calculs relativement faible.----------ABSTRACT Brain-Machine Interfaces (BMIs) are increasingly important in biomedical research and health care applications, such as medical laboratory tests and analyses, cerebrology, and complementary treatment of neuromuscular disorders. BMIs, and neural recording devices in particular, rely heavily on signal processing methods to provide users with nformation. Current neural recording devices integrate many parallel channels, which produce a huge amount of data that is difficult to transmit, cannot guarantee the quality of the recorded signals and may limit on-chip signal processing capabilities. An improved signal processing system is needed to ensure that neural recording devices can cope with rapidly increasing data size and accuracy requirements. This thesis focused on two signal processing approaches – signal compression and reduction – for neural recording devices. First, compressed sensing (CS) was employed for neural signal compression, using a minimum Euclidean or Manhattan distance cluster-based (MDC) deterministic sensing matrix. Sparse and non-sparse neural signals were substantially compressed and later reconstructed with minimal error using the built MDC matrix. Neural signal reduction required spike detection and sorting, which was conducted using a Bayesian inference-based template matching (BBTM) method. Compared with amplitude-based, energy-based, and some other template matching methods, BBTM has high detection accuracy, especially for low signal-to-noise ratio signals, and can separate overlapping spikes acquired from different neurons. In addition, BBTM can automatically generate the needed templates with relatively low system complexity. Finally, a digital online adaptive neural signal processing system, including spike detector and CS-based compressor, was designed. Both single and multi-channel solutions were implemented and evaluated. Compared with the signal processing systems in current use, the proposed signal processing system can efficiently compress a large number of sampled data and recover original signals with a small reconstruction error; also it has low power consumption and a small silicon area. The completed prototype shows considerable promise for application in a wide range of neural recording interfaces