A fast and low-power microelectromechanical system-based non-volatile memory device

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices

Top-down Si nanowire technology in discrete charge storage nonvolatile memory application

Ph.DDOCTOR OF PHILOSOPH

Etude d'architectures et d'empilements innovants de mémoires Split-Gate (grille séparée) à couche de piégeage discret

Du fait de l'augmentation de la demande de produits pour les applications grand public, industrielles et automobiles, des mémoires embarquées fiables et à faible coût de fabrication sont de plus en plus demandées. Dans ce contexte, les mémoires split-gate à piégeage discret sont proposées pour des microcontrôleurs. Elles combinent l'avantage d'une couche de stockage discrète et de la con guration split-gate. Durant ce travail de recherche, des mémoires split-gate à couche de piégeage discret ayant des longueurs de grille de 20nm sont présentées pour la première fois. Celles-ci on été réalisées avec des nanocristaux de silicium (Si-nc), du nitrure de silicium (SiN) ou un hybride Si-nc/SiN avec diélectrique de control de type SiO2 ou AlO et sont comparées en termes de performances lors des procédures d'eff acement et de rétention. Ensuite, la miniaturisation des mémoires split-gate à piégeage de charge est étudié, en particulier au travers de l'impact de la réduction de la longueur de grille sur la fenêtre de mémorisation, la rétention et la consommation. Le rôle des défauts dans le diélectrique de contrôle (alumine) utilisé dans les mémoires de type TANOS a été étudié. Des travaux ont été menés pour déterminer l'origine des pièges dans ce matériau, par le biais de la simulation atomistique ainsi que d'analyses physico-chimiques précises. Nous avons montré que la concentration de pièges dans AlO pouvait être réduite par ajustement des conditions de procédé de fabrication, débouchant ainsi sur l'amélioration de la rétention dans les mémoires à piégeage de charge. Ce résultat est convenable pour les applications de type embarquéDue to the increasing demand for consumer, industrial and automotive products, highly reliable, and low integration cost embedded memories are more and more required. In this context, split-gate charge trap memories were proposed for microcontroller products, combining the advantage of a discrete storage layer and of the split-gate con guration. In this thesis, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-nc), or silicon nitride (SiN) and hybrid Si-nc/SiN based split-gate memories, with SiO2 or AlO control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. We thus studied the role of defects on alumina control dielectric employed in TANOS-like memory. We used atomistic simulation, consolidated by a detailed alumina physico-chemical material analysis, to investigate the origin of traps in alumina. We showed that the trap concentration in AlO can be decreased by adjusting the process conditions leading to improved retention behaviour in charge trap memory, suitable for embedded applications.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 박병국.Exploding demands for mobile devices induce the drastic expansion of the market of NAND flash memory as high density storage devices. Three-dimensional (3D) NAND flash memory paved a new way of increasing the memory capacity by stacking cells in three-dimension. For stacked NAND flash memory, the thickness of ONO (memory dielectric layers) is a roadblock in scaling-down of the minimum feature size, because channel diameter can be scaled down to < 20 nm. However, it is challenging to reduce the thickness of oxide-nitride-oxide (ONO) layer, since the charge trapping properties degrade when the Si3N4 is made thinner. .In this thesis, the channel stacked NAND flash memory array (CSTAR) with high-κ charge trapping layer for high scalability is proposed. To adopt high-κ layer into 3D NAND, its memory characteristics were evaluated with capacitors and gate-all-around flash memory devices. Finally, 4-layer channel stacked memory with high-κ layer was successfully fabricated and characterized. Recent trend of nonvolatile memories are introduced and the overview of 3D stacked NAND flash memory technology is presented in Chapter 1 and 2. In Chapter 3, the memory characteristics of high-κ layer were evaluated with fabricated capacitors and flash memory devices. In Chapter 4, fabrication process and electrical characteristics of CSTAR with high-κ are shown. With the comparison with previous works using ONO layer, CSTAR with high-κ is evaluated. In Chapter 5, the novel operation method of CSTAR is presented. Using TCAD and measurement, a newly designed operation method is verifiedChapter 1 Introduction 1 1.1 Flash Memory Technology 1 1.2 Flash Memory Unit Cell and Array Structure 6 1.3 NAND Cell Operation 13 1.4 Charge Trap Flash Memory 25 Chapter 2 3-D Stacked NAND Flash Memory 28 2.2 Examination of Previous 3-D Stacked NAND Flash 28 2.2.1 Gate Stack Type 3-D NAND Flash Memory 28 2.2.2 Channel Stack Type 3-D NAND Flash Memory 36 2.2.3 Comparison between the Gate Stack Type and the Channel Stack Type 45 Chapter 3 Channel Stacked NAND Flash Memory with high- Charge Trapping Layer 48 3.1 Introduction 48 3.2 Memory Characteristics of HfO2 52 3.3 Fabrication of Nanowire Memory Devices with high-κ Dielectric Layer 56 Chapter 4 Fabrication of Channel Stacked NAND Flash Memory with High-κ 66 4.1 Introduction 66 4.2 Fabrication Method 67 4.3 Key Process Steps of CSTAR with high-κ 72 4.3.1 Single Crystalline Silicon Channel 72 4.3.2 Fin Patterning 74 4.3.3 Stacked Nanowires 76 4.4 Measurement Results 81 4.5 Comparison with Previous Works 88 Chapter 5 Novel Program Operation in CSTAR 92 5.1 Introduction. 92 5.2 Simulation Results 93 5.3 Measurement Results 103 Chapter 6 Conclusions 106 Bibliography 108 Abstract in Korean 116 List of Publications 118Docto

Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

Application of novel gate materials for performance improvement in flash memory devices

Ph.DDOCTOR OF PHILOSOPH

Organic molecular floating gate memories

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 42-45).Flash memory devices dominate the non-volatile memory market, with device structures that utilize charge storage in polysilicon floating gates imbedded in insulating silicon oxide films'. As demands for high storage density, high chip memory capacity, and decreasing process costs continue to mount, conventional flash memory has found it challenging to continue scaling and it may reach fundamental scaling limits because of the minimum tunnel oxide thickness and poor charge retention due to defects in the tunneling oxide, necessitating modification in the implementation of the flash memory technology . In this study nano-segmented floating gate memories consisting of a uniform set of identical organic dye molecules were fabricated and evaluated for potential use as programmable charge storage and charge retention elements in a future flash memory technology. Viability of molecular thin films to serve as an energetically-uniform set of ~1nm in size charge- retaining sites is tested on a series of molecular materials, the best performing of which are thermally evaporated thin films of 3,4,9,10- perylenetetracarboxylic bis-benzimidazole (PTCBI). The initial results show device durability over 105 program/erase cycles, with hysteresis window of up to 3.3V, corresponding to charge storage density as high as 5 x 1012 cm2. Data shows that charge retention is improved for molecular films with lower carrier mobility, which for the first time experimentally confirms in a coherent material set that inhibiting charge transport by nano-segmented floating-gate structures benefits the memory retention. These results show a first step towards a possible approach to miniaturization of non-volatile memory by using molecules as segmented charge storage elements in the floating gate flash memory technology.by Sarah Paydavosi.S.M