899 research outputs found
Implementable Wireless Access for B3G Networks - III: Complexity Reducing Transceiver Structures
This article presents a comprehensive overview of some of the research conducted within Mobile VCE’s Core Wireless Access Research Programme,1 a key focus of which has naturally been on MIMO transceivers. The series of articles offers a coherent view of how the work was structured and comprises a compilation of material that has been presented in detail elsewhere (see references within the article). In this article MIMO channel measurements, analysis, and modeling, which were presented previously in the first article in this series of four, are utilized to develop compact and distributed antenna arrays. Parallel activities led to research into low-complexity MIMO single-user spacetime coding techniques, as well as SISO and MIMO multi-user CDMA-based transceivers for B3G systems. As well as feeding into the industry’s in-house research program, significant extensions of this work are now in hand, within Mobile VCE’s own core activity, aiming toward securing major improvements in delivery efficiency in future wireless systems through crosslayer operation
Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems
In this paper, implementation of a detector with parallel partial candidate-search algorithm is described. Two fully independent partial candidate search processes are simultaneously employed for two groups of transmit antennas based
on QR decomposition (QRD) and QL decomposition (QLD) of a multiple-input multiple-output (MIMO) channel matrix. By using separate simultaneous candidate searching processes, the proposed implementation of QRD-QLD searching-based sphere detector provides a smaller latency and a lower computational complexity
than the original QRD-M detector for similar error-rate performance in wireless communications systems employing four transmit and four receive antennas with 16-QAM or 64-QAM constellation size. It is shown that in coded MIMO orthogonal
frequency division multiplexing (MIMO OFDM) systems, the detection latency and computational complexity of a receiver can be substantially reduced by using the proposed QRD-QLD detector implementation. The QRD-QLD-based sphere detector is also implemented using Field Programmable Gate Array (FPGA) and application specific integrated circuit (ASIC), and its hardware design complexity is compared with that of other sphere detectors reported in the literature.Nokia Renesas MobileTexas InstrumentsXilinxNational Science Foundatio
Probabilistically Bounded Soft Sphere Detection for MIMO-OFDM Receivers: Algorithm and System Architecture
Iterative soft detection and channel decoding for MIMO OFDM downlink receivers is studied in this work. Proposed inner soft sphere detection employs a variable upper bound for number of candidates per transmit antenna and utilizes the breath-first candidate-search algorithm. Upper bounds are based on probability distribution of the number of candidates found inside the spherical region formed around the received symbol-vector. Detection accuracy of unbounded breadth-first candidate search is preserved while significant reduction of the search latency and area cost is achieved. This probabilistically bounded candidate-search algorithm improves error-rate performance of non-probabilistically bounded soft sphere detection algorithms,
while providing smaller detection latency with same hardware resources. Prototype architecture of soft sphere detector is synthesized on Xilinx FPGA and for an ASIC design. Using area-cost of a single soft sphere detector, a level of processing parallelism required to achieve targeted high data rates for future wireless systems (for example, 1 Gbps data rate) is determined.NokiaNational Science Foundatio
Enabling VLSI processing blocks for MIMO-OFDM Communications
Multi-input multi-output (MIMO) systems combined
with orthogonal frequency-division multiplexing (OFDM)
gained a wide popularity in wireless applications due to the
potential of providing increased channel capacity and robustness
against multipath fading channels. However these advantages
come at the cost of a very high processing complexity and
the efficient implementation of MIMO-OFDM receivers is today
a major research topic. In this paper, efficient architectures
are proposed for the hardware implementation of the main
building blocks of a MIMO-OFDM receiver. A sphere decoder
architecture flexible to different modulation without any loss in
BER performance is presented while the proposed matrix factorization
implementation allows to achieve the highest throughput
specified in the IEEE 802.11n standard. Finally a novel sphere
decoder approach is presented, which allows for the realization of
new golden space time trellis coded modulation (GST-TCM)
scheme. Implementation cost and offered throughput are provided
for the proposed architectures synthesized on a 0.13 CMOS
standard cell technology or on advanced FPGA devices
Adaptive and Iterative Multi-Branch MMSE Decision Feedback Detection Algorithms for MIMO Systems
In this work, decision feedback (DF) detection algorithms based on multiple
processing branches for multi-input multi-output (MIMO) spatial multiplexing
systems are proposed. The proposed detector employs multiple cancellation
branches with receive filters that are obtained from a common matrix inverse
and achieves a performance close to the maximum likelihood detector (MLD).
Constrained minimum mean-squared error (MMSE) receive filters designed with
constraints on the shape and magnitude of the feedback filters for the
multi-branch MMSE DF (MB-MMSE-DF) receivers are presented. An adaptive
implementation of the proposed MB-MMSE-DF detector is developed along with a
recursive least squares-type algorithm for estimating the parameters of the
receive filters when the channel is time-varying. A soft-output version of the
MB-MMSE-DF detector is also proposed as a component of an iterative detection
and decoding receiver structure. A computational complexity analysis shows that
the MB-MMSE-DF detector does not require a significant additional complexity
over the conventional MMSE-DF detector, whereas a diversity analysis discusses
the diversity order achieved by the MB-MMSE-DF detector. Simulation results
show that the MB-MMSE-DF detector achieves a performance superior to existing
suboptimal detectors and close to the MLD, while requiring significantly lower
complexity.Comment: 10 figures, 3 tables; IEEE Transactions on Wireless Communications,
201
Soft Sphere Detection with Bounded Search for High-Throughput MIMO Receivers
We propose a soft sphere detection algorithm where search-bounds are determined based on the distribution of candidates found inside the sphere for different search levels. Detection accuracy of unbounded search is preserved while
significant saving of memory space and reduction of latency is achieved. This probabilistic search algorithm provides significantly better frame-error rate performance than the soft K-best solution and has comparable performance and smaller computational complexity than the bounded depth-first search method.
Techniques for efficient and flexible architecture design of soft sphere detectors are also presented. The estimated hardware cost is lower than the hardware cost of other soft sphere detectors from the literature, while high detection throughput per channel use is achieved
Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design
This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and channel decoding (JSCD) schemes for low-power SoCs used in portable multimedia systems, 2) efficient on-chip interconnect architecture for massive multimedia data streaming on multiprocessor SoCs (MPSoCs), and 3) data processing architecture for low-power SoCs in distributed sensor network (DSS) systems and its implementation.
The first part includes a low-power embedded low density parity check code (LDPC) - H.264 joint decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). A low-power multiple-input multiple-output (MIMO) and H.264 video joint detector/decoder design that minimizes energy for portable, wireless embedded systems is also designed.
In the second part, a link-level quality of service (QoS) scheme using unequal error protection (UEP) for low-power network-on-chip (NoC) and low latency on-chip network designs for MPSoCs is proposed. This part contains WaveSync, a low-latency focused network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs and a simultaneous dual-path routing (SDPR) scheme utilizing path diversity present in typical mesh topology network-on-chips. SDPR is akin to having a higher link width but without the significant hardware overhead associated with simple bus width scaling.
The last part shows data processing unit designs for embedded SoCs. We propose a data processing and control logic design for a new radiation detection sensor system generating data at or above Peta-bits-per-second level. Implementation results show that the intended clock rate is achieved within the power target of less than 200mW. We also present a digital signal processing (DSP) accelerator supporting configurable MAC, FFT, FIR, and 3-D cross product operations for embedded SoCs. It consumes 12.35mW along with 0.167mm2 area at 333MHz
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