Diseño e implementación de un microprocesador de propósito específico

Este documento pretende compartir la experiencia del diseño de un procesador y su implementación en una FPGA (Spartan 3E – 100E), mostrando las características generales que debe tener el procesador para que sea lo suficientemente flexible, y que herramientas adicionales se deben crear para facilitar sus pruebas e implementación

Diseño e implementación de un microprocesador de propósito específico

Este documento pretende compartir la experiencia del diseño de un procesador y su implementación en una FPGA (Spartan 3E – 100E), mostrando las características generales que debe tener el procesador para que sea lo suficientemente flexible, y que herramientas adicionales se deben crear para facilitar sus pruebas e implementación

Balancing Design Options with Sherpa

Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, there have been several major projects that attempt to automate the process of transforming a predetermined processor configuration into a low level description for fabrication. These projects either leave the specification of the processor to the designer, which can be a significant engineering burden, or handle it in a fully automated fashion, which completely removes the designer from the loop. In this paper we introduce a technique for guiding the design and optimization of application specific processors. The goal of the Sherpa design framework is to automate certain design tasks and provide early feedback to help the designer navigate their way through the architecture design space. Our approach is to decompose the overall problem of choosing an optimal architecture into a set of sub-problems that are, to the first order, independent. For each subproblem, we create a model that relates performance to area. From this, we build a constraint system that can be solved using integer-linear programming techniques, and arrive at an ideal parameter selection for all architectural components. Our approach only takes a few minutes to explore the design space allowing the designer or compiler to see the potential benefits of optimizations rapidly. We show that the expected performance using our model correlates strongly to detailed pipeline simulations, and present results showing design tradeoffs for several different benchmarks

Generator of Instruction Set Manual

Tato bakalářská práce se zabývá vytvořením generátoru manuálu instrukční sady, který je součástí projektu Lissom. Model mikroprocesoru je popsán v jazyce ISAC pro popis architektury mikroprocesoru i instrukční sady, kde si vývojář k jednotlivým deklaracím doplní speciálně formátované komentáře. Na základě těchto údajů jsou do manuálu vybrány pouze patřičné informace a nalezeny vztahy mezi nimi. Pro generování instrukcí je využit mezijazyk pro generátor překladače jazyka C. Výsledný dokument manuálu je uložen ve formátu RTF a obsahuje dvě části. V první je uveden přehled všech zdrojů procesoru a ve druhé je seznam všech instrukcí.This bachelor thesis describes the design and implementation of a generator of instruction set manual, that is a part of the Lissom project. Model of microprocessor is described using architecture and instruction set description language ISAC with added special marked comments to each one declaration. From this source of data useful information and relationships between them are selected for manual. The source of data for generating of instructions is the intermediate-language for generator of C language compiler. The output generated manual document is saved as RTF file and it contains two parts. First part includes summary of all microprocessor's resources and second part contains the list of all instructions.