Reducing the power consumption in LTE-advanced wireless access networks by a capacity based deployment tool

As both the bit rate required by applications on mobile devices and the number of those mobile devices are steadily growing, wireless access networks need to be expanded. As wireless networks also consume a lot of energy, it is important to develop energy-efficient wireless access networks in the near future. In this study, a capacity-based deployment tool for the design of energy-efficient wireless access networks is proposed. Capacity-based means that the network responds to the instantaneous bit rate requirements of the users active in the selected area. To the best of our knowledge, such a deployment tool for energy-efficient wireless access networks has never been presented before. This deployment tool is applied to a realistic case in Ghent, Belgium, to investigate three main functionalities incorporated in LTE-Advanced: carrier aggregation, heterogeneous deployments, and Multiple-Input Multiple-Output (MIMO). The results show that it is recommended to introduce femtocell base stations, supporting both MIMO and carrier aggregation, into the network (heterogeneous deployment) to reduce the network's power consumption. For the selected area and the assumptions made, this results in a power consumption reduction up to 70%. Introducing femtocell base stations without MIMO and carrier aggregation can already result in a significant power consumption reduction of 38%

Randomized cache placement for eliminating conflicts

Applications with regular patterns of memory access can experience high levels of cache conflict misses. In shared-memory multiprocessors conflict misses can be increased significantly by the data transpositions required for parallelization. Techniques such as blocking which are introduced within a single thread to improve locality, can result in yet more conflict misses. The tension between minimizing cache conflicts and the other transformations needed for efficient parallelization leads to complex optimization problems for parallelizing compilers. This paper shows how the introduction of a pseudorandom element into the cache index function can effectively eliminate repetitive conflict misses and produce a cache where miss ratio depends solely on working set behavior. We examine the impact of pseudorandom cache indexing on processor cycle times and present practical solutions to some of the major implementation issues for this type of cache. Our conclusions are supported by simulations of a superscalar out-of-order processor executing the SPEC95 benchmarks, as well as from cache simulations of individual loop kernels to illustrate specific effects. We present measurements of instructions committed per cycle (IPC) when comparing the performance of different cache architectures on whole-program benchmarks such as the SPEC95 suite.Peer ReviewedPostprint (published version

Virtual-physical registers

A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed all evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 19% increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach.Peer ReviewedPostprint (published version