352 research outputs found
Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines
Journal ArticleAbstract This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gC controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large design space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burst-mode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient single-cube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor - more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before
NASA Space Engineering Research Center Symposium on VLSI Design
The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers
Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963
Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication
Automatic test pattern generation for asynchronous circuits
The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer
scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes
inevitably part of the design process; a technique called design for test (DFT). Asynchronous
circuits have a number of desirable properties making them suitable for the challenges posed
by modern technologies, but are severely limited by the unavailability of EDA tools for DFT
and automatic test-pattern generation (ATPG).
This thesis is motivated towards developing test generation methodologies for asynchronous
circuits. In total four methods were developed which are aimed at two different fault models:
stuck-at faults at the basic logic gate level and transistor-level faults. The methods were
evaluated using a set of benchmark circuits and compared favorably to previously published
work.
First, ABALLAST is a partial-scan DFT method adapting the well-known BALLAST technique
for asynchronous circuits where balanced structures are used to guide the selection of
the state-holding elements that will be scanned. The test inputs are automatically provided
by a novel test pattern generator, which uses time frame unrolling to deal with the remaining,
non-scanned sequential C-elements. The second method, called AGLOB, uses algorithms
from strongly-connected components in graph graph theory as a method for finding the optimal
position of breaking the loops in the asynchronous circuit and adding scan registers. The
corresponding ATPG method converts cyclic circuits into acyclic for which standard tools can
provide test patterns. These patterns are then automatically converted for use in the original
cyclic circuits. The third method, ASCP, employs a new cycle enumeration method to find the
loops present in a circuit. Enumerated cycles are then processed using an efficient set covering
heuristic to select the scan elements for the circuit to be tested.Applying these methods to
the benchmark circuits shows an improvement in fault coverage compared to previous work,
which, for some circuits, was substantial. As no single method consistently outperforms the
others in all benchmarks, they are all valuable as a designer’s suite of tools for testing. Moreover,
since they are all scan-based, they are compatible and thus can be simultaneously used in
different parts of a larger circuit.
In the final method, ATRANTE, the main motivation of developing ATPG is supplemented by
transistor level test generation. It is developed for asynchronous circuits designed using a State
Transition Graph (STG) as their specification. The transistor-level circuit faults are efficiently
mapped onto faults that modify the original STG. For each potential STG fault, the ATPG tool
provides a sequence of test vectors that expose the difference in behavior to the output ports.
The fault coverage obtained was 52-72 % higher than the coverage obtained using the gate
level tests. Overall, four different design for test (DFT) methods for automatic test pattern generation
(ATPG) for asynchronous circuits at both gate and transistor level were introduced in this thesis.
A circuit extraction method for representing the asynchronous circuits at a higher level of
abstraction was also implemented.
Developing new methods for the test generation of asynchronous circuits in this thesis facilitates
the test generation for asynchronous designs using the CAD tools available for testing the
synchronous designs. Lessons learned and the research questions raised due to this work will
impact the future work to probe the possibilities of developing robust CAD tools for testing the
future asynchronous designs
JUNO Conceptual Design Report
The Jiangmen Underground Neutrino Observatory (JUNO) is proposed to determine
the neutrino mass hierarchy using an underground liquid scintillator detector.
It is located 53 km away from both Yangjiang and Taishan Nuclear Power Plants
in Guangdong, China. The experimental hall, spanning more than 50 meters, is
under a granite mountain of over 700 m overburden. Within six years of running,
the detection of reactor antineutrinos can resolve the neutrino mass hierarchy
at a confidence level of 3-4, and determine neutrino oscillation
parameters , , and to
an accuracy of better than 1%. The JUNO detector can be also used to study
terrestrial and extra-terrestrial neutrinos and new physics beyond the Standard
Model. The central detector contains 20,000 tons liquid scintillator with an
acrylic sphere of 35 m in diameter. 17,000 508-mm diameter PMTs with high
quantum efficiency provide 75% optical coverage. The current choice of
the liquid scintillator is: linear alkyl benzene (LAB) as the solvent, plus PPO
as the scintillation fluor and a wavelength-shifter (Bis-MSB). The number of
detected photoelectrons per MeV is larger than 1,100 and the energy resolution
is expected to be 3% at 1 MeV. The calibration system is designed to deploy
multiple sources to cover the entire energy range of reactor antineutrinos, and
to achieve a full-volume position coverage inside the detector. The veto system
is used for muon detection, muon induced background study and reduction. It
consists of a Water Cherenkov detector and a Top Tracker system. The readout
system, the detector control system and the offline system insure efficient and
stable data acquisition and processing.Comment: 328 pages, 211 figure
Optimisation of Mobile Communication Networks - OMCO NET
The mini conference “Optimisation of Mobile Communication Networks” focuses on advanced methods for search and optimisation applied to wireless communication networks. It is sponsored by Research & Enterprise Fund Southampton Solent University.
The conference strives to widen knowledge on advanced search methods capable of optimisation of wireless communications networks. The aim is to provide a forum for exchange of recent knowledge, new ideas and trends in this progressive and challenging area. The conference will popularise new successful approaches on resolving hard tasks such as minimisation of transmit power, cooperative and optimal routing
The Fifth NASA Symposium on VLSI Design
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design
Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines
This paper presents a new approach to two-level hazardfree logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gC controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large design space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burst-mode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient singlecube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor — more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before.
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