A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Mixed-signal CNN array chips for image processing

Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many challenging problems to analog designers. This is basically due to the fact that large silicon area means large development cost, large spatial deviations of design parameters and low production yield. CNN designers must face different issues to keep reasonable enough accuracy level and production yield together with reasonably low development cost in their design of large CNN chips. This paper outlines some of these major issues and their solutions

Generating All Two-MOS-Transistor Amplifiers Leads to New Wide-Band LNAs

This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-µm CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V

High-speed communication circuits: voltage control oscillators and VCO-derived filters

Voltage Controlled Oscillators (VCO) and filters are the two main topics of focus in this dissertation.;A temperature and process compensated VCO, which is designed to operate at 2 GHz, and whose frequency variation due to incoming data is limited to 1% of its center frequency was presented. The test results show that, without process changes present, the frequency variation due to a temperature change over 0°C to 100°C is around 1.1% of its center frequency. This is a reduction of a factor of 10 when compared to the temperature variation of a conventional VCO.;A new method of designing continuous-time monolithic filters derived from well-known voltage controlled oscillators (VCOs) was introduced. These VCO-derived filters are capable of operating at very high frequencies in standard CMOS processes. Prototype low-pass and band-pass filters designed in a TSMC 0.25 mum process are discussed. Simulation results for the low-pass filter designed for a cutoff frequency of 4.3 GHz show a THD of -40 dB for a 200 mV peak-peak sinusoidal input. The band-pass filter has a resonant frequency programmable from 2.3 GHz to 3.1 GHz, a programmable Q from 3 to 85, and mid-band THD of -40 dB for an 80 mV peak-peak sinusoidal input signal.;A third contribution in this dissertation was the design of a new current mirror with accurate mirror gain for low beta bipolar transistors. High mirror gain accuracy is achieved by using a split-collector transistor to compensate for base currents of the source-coupled

Design of a single-chip pH sensor using a conventional 0.6-μm CMOS process

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6-/spl μm CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a large threshold voltage that is postulated to be caused by a trapped charge on the floating gate. Ultraviolet radiation and bulk-substrate biasing is used to permanently modify the threshold voltage so that the ISFET can be used in a battery-operated circuit. A novel post-processing method using a single layer of photoresist is used to define the sensing areas and to provide robust encapsulation for the chip. The complete circuit, operating from a single 3-V supply, provides an output voltage proportional to pH and can be powered down when not required

Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing"

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 ¿m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30

Negative Bias Temperature Instability (NBTI) Monitoring and Mitigation Technique for MOSFET

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