Compressed Passive Macromodeling

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed techniqu

Parallel Algorithms for Time and Frequency Domain Circuit Simulation

As a most critical form of pre-silicon verification, transistor-level circuit simulation is an indispensable step before committing to an expensive manufacturing process. However, considering the nature of circuit simulation, it can be computationally expensive, especially for ever-larger transistor circuits with more complex device models. Therefore, it is becoming increasingly desirable to accelerate circuit simulation. On the other hand, the emergence of multi-core machines offers a promising solution to circuit simulation besides the known application of distributed-memory clustered computing platforms, which provides abundant hardware computing resources. This research addresses the limitations of traditional serial circuit simulations and proposes new techniques for both time-domain and frequency-domain parallel circuit simulations. For time-domain simulation, this dissertation presents a parallel transient simulation methodology. This new approach, called WavePipe, exploits coarse-grained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step, the latter performs predictive computing along the forward direction. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardizing convergence and accuracy. As a coarse-grained parallel approach, it requires low parallel programming effort, furthermore it creates new avenues to have a full utilization of increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions. This dissertation also exploits the recently developed explicit telescopic projective integration method for efficient parallel transient circuit simulation by addressing the stability limitation of explicit numerical integration. The new method allows the effective time step controlled by accuracy requirement instead of stability limitation. Therefore, it not only leads to noticeable efficiency improvement, but also lends itself to straightforward parallelization due to its explicit nature. For frequency-domain simulation, this dissertation presents a parallel harmonic balance approach, applicable to the steady-state and envelope-following analyses of both driven and autonomous circuits. The new approach is centered on a naturally-parallelizable preconditioning technique that speeds up the core computation in harmonic balance based analysis. The proposed method facilitates parallel computing via the use of domain knowledge and simplifies parallel programming compared with fine-grained strategies. As a result, favorable runtime speedups are achieved

Accelerated Waveform Methods for Parallel Transient Simulation of Semiconductor Devices

In this paper e compare accelerated waveform relax- ation algorithms to pointwise methods for the transient simulation of semiconductor devices on parallel machines. Experimental results are presented for simula- tions on small clusters of workstations and on an Intel iPSC/860. The results show that accelerated waveform methods are competitive with standard pointwise methods on serial machines, but are significantly faster on loosely-coupled MIMD machines

Accelerated Waveform Methods for Parallel Transient Simulation of Semiconductor Devices

In this paper we compare accelerated waveform relaxation algorithms to pointwise methods for the transient simulation of semiconductor devices on parallel machines. Experimental results are presented for simulations on small clusters of workstations and on an Intel iPSC/860. The results show that accelerated waveform methods are competitive with standard pointwise methods on serial machines, but are significantly faster on loosely-coupled MIMD machines. 1 Introduction The computational expense and growing importance of performing semiconductor device transient simulation, along with the increasing availability of parallel computers, suggest that parallel algorithms be developed and used for these simulation problems. Although SIMD type parallel machines have been shown to be effective for device transient simulation [1, 2], as MIMD machines become increasingly more popular and cost-effective, it is important that efficient algorithms be developed for them as well. To obtain highest pe..