GPU implementation of bitplane coding with parallel coefficient processing for high performance image compression

The fast compression of images is a requisite in many applications like TV production, teleconferencing, or digital cinema. Many of the algorithms employed in current image compression standards are inherently sequential. High performance implementations of such algorithms often require specialized hardware like field integrated gate arrays. Graphics Processing Units (GPUs) do not commonly achieve high performance on these algorithms because they do not exhibit fine-grain parallelism. Our previous work introduced a new core algorithm for wavelet-based image coding systems. It is tailored for massive parallel architectures. It is called bitplane coding with parallel coefficient processing (BPC-PaCo). This paper introduces the first high performance, GPU-based implementation of BPC-PaCo. A detailed analysis of the algorithm aids its implementation in the GPU. The main insights behind the proposed codec are an efficient thread-to-data mapping, a smart memory management, and the use of efficient cooperation mechanisms to enable inter-thread communication. Experimental results indicate that the proposed implementation matches the requirements for high resolution (4 K) digital cinema in real time, yielding speedups of 30x with respect to the fastest implementations of current compression standards. Also, a power consumption evaluation shows that our implementation consumes 40 x less energy for equivalent performance than state-of-the-art methods

Implementation of the DWT in a GPU through a register-based strategy

The release of the CUDA Kepler architecture in March 2012 has provided Nvidia GPUs with a larger register memory space and instructions for the communication of registers among threads. This facilitates a new programming strategy that utilizes registers for data sharing and reusing in detriment of the shared memory. Such a programming strategy can significantly improve the performance of applications that reuse data heavily. This paper presents a register-based implementation of the Discrete Wavelet Transform (DWT), the prevailing data decorrelation technique in the field of image coding. Experimental results indicate that the proposed method is, at least, four times faster than the best GPU implementation of the DWT found in the literature. Furthermore, theoretical analysis coincide with experimental tests in proving that the execution times achieved by the proposed implementation are close to the GPU's performance limits

Artificial Intelligence Ethics, governance and policy challenges. Report of a CEPS Task Force, February 2019

Like an unannounced guest, artificial intelligence (AI) has suddenly emerged from nerdy discussions in university labs and begun to infiltrate larger venues and policy circles around the globe. Everywhere, and particularly in Europe, the debate has been tainted by much noise and fear, as evidenced in the European Parliament’s resounding report on civil law rules for robotics, in which Mary Shelley’s Frankenstein is evoked on the opening page (European Parliament, 2016). At countless seminars, workshops and conferences, self-proclaimed “experts” voice concerns about robots taking our jobs, disrupting our social interactions, manipulating public opinion and political elections, and ultimately taking over the world by dismissing human beings, once and for all, as redundant and inefficient legacies of the past