44 research outputs found

    Application of learning algorithms to traffic management in integrated services networks.

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    SIGLEAvailable from British Library Document Supply Centre-DSC:DXN027131 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

    A hybrid queueing model for fast broadband networking simulation

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    PhDThis research focuses on the investigation of a fast simulation method for broadband telecommunication networks, such as ATM networks and IP networks. As a result of this research, a hybrid simulation model is proposed, which combines the analytical modelling and event-driven simulation modelling to speeding up the overall simulation. The division between foreground and background traffic and the way of dealing with these different types of traffic to achieve improvement in simulation time is the major contribution reported in this thesis. Background traffic is present to ensure that proper buffering behaviour is included during the course of the simulation experiments, but only the foreground traffic of interest is simulated, unlike traditional simulation techniques. Foreground and background traffic are dealt with in a different way. To avoid the need for extra events on the event list, and the processing overhead, associated with the background traffic, the novel technique investigated in this research is to remove the background traffic completely, adjusting the service time of the queues for the background traffic to compensate (in most cases, the service time for the foreground traffic will increase). By removing the background traffic from the event-driven simulator the number of cell processing events dealt with is reduced drastically. Validation of this approach shows that, overall, the method works well, but the simulation using this method does have some differences compared with experimental results on a testbed. The reason for this is mainly because of the assumptions behind the analytical model that make the modelling tractable. Hence, the analytical model needs to be adjusted. This is done by having a neural network trained to learn the relationship between the input traffic parameters and the output difference between the proposed model and the testbed. Following this training, simulations can be run using the output of the neural network to adjust the analytical model for those particular traffic conditions. The approach is applied to cell scale and burst scale queueing to simulate an ATM switch, and it is also used to simulate an IP router. In all the applications, the method ensures a fast simulation as well as an accurate result

    Work-conserving WRR-CSVP resource allocation in ATM networks

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    Parallel simulation techniques for telecommunication network modelling

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    In this thesis, we consider the application of parallel simulation to the performance modelling of telecommunication networks. A largely automated approach was first explored using a parallelizing compiler to speed up the simulation of simple models of circuit-switched networks. This yielded reasonable results for relatively little effort compared with other approaches. However, more complex simulation models of packet- and cell-based telecommunication networks, requiring the use of discrete event techniques, need an alternative approach. A critical review of parallel discrete event simulation indicated that a distributed model components approach using conservative or optimistic synchronization would be worth exploring. Experiments were therefore conducted using simulation models of queuing networks and Asynchronous Transfer Mode (ATM) networks to explore the potential speed-up possible using this approach. Specifically, it is shown that these techniques can be used successfully to speed-up the execution of useful telecommunication network simulations. A detailed investigation has demonstrated that conservative synchronization performs very well for applications with good look ahead properties and sufficient message traffic density and, given such properties, will significantly outperform optimistic synchronization. Optimistic synchronization, however, gives reasonable speed-up for models with a wider range of such properties and can be optimized for speed-up and memory usage at run time. Thus, it is confirmed as being more generally applicable particularly as model development is somewhat easier than for conservative synchronization. This has to be balanced against the more difficult task of developing and debugging an optimistic synchronization kernel and the application models

    Resource allocation and congestion control strategies for networked unmanned systems

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    It is generally agreed that communication is a critical technological factor in designing networked unmanned systems (NUS) that consist of a large number of heterogeneous assets/nodes that may be configured in ad-hoc fashion and that incorporate intricate architectures. In order to successfully carry out the NUS missions, communication among assets need to be accomplished efficiently. In contrast with conventional networks, NUSs have specific features that may render communication more complex. The main distinct characteristics of NUS are as follows: (a) heterogeneity of assets in terms of resources, (b) multiple topologies that can be fully-connected, (c) real-time requirements imposed by delivery timeliness of messages under evolving and uncertain environments, (d) unknown and random time-delays that may degrade the closed-loop dynamics performance, (e) bandwidth constraints reflecting differences in assets behavior and dynamics, and (f) protocol limitations for complying with the wireless features of these networks. The NUS system consists of clusters each having three nodes, namely, a sensor, a decision-maker, and an actuator. Inspired by networked control systems (NCS), we introduced a generic framework for NUSs. Using the fluid flow model (FFM), the overall dynamical model of our network cluster is derived as a time-delay dependent system. The following three main issues are investigated in this thesis, bandwidth allocation, an integrated bandwidth allocation and flow rate control, and congestion control. To demonstrate the difficulty of addressing the bandwidth allocation control problem, a standard PID is implemented for our network cluster. It is shown that in presence of feedback loops and time-delays in the network, this controller induces flow oscillations and consequently, in the worst-case scenario, network instability. To address this problem, nonlinear control strategies are proposed instead. These strategies are evaluated subject to presence of unknown delays and measurable/estimated input traffic. For different network configurations, the error dynamics of the entire controlled cluster is derived and sufficient stability conditions are obtained. In addition, our proposed bandwidth allocation control strategy is evaluated when the NUS assets are assumed to be mobile. The bandwidth allocation problem is often studied in an integrated fashion with the flow rate control and the connection admission control (CAC). In fact, due to importance of interaction of various components, design of the entire control system is often more promising than optimization of individual components. In this thesis, several robust integrated bandwidth allocation and flow rate control strategies are proposed. The third issue that is investigated in this thesis is the congestion control for differentiated-services (DiffServ) networks. In our proposed congestion control strategies, the buffer queue length is used as a feedback information to control locally the queue length of each buffer by acting on the bandwidth and simultaneously a feedback signaling notifies the ordinary sources regarding the allowed maximum rate. Using sliding mode generalized variable structure control techniques (SM-GVSC), two congestion control approaches are proposed, namely, the non degenerate and degenerate GVS control approaches. By adopting decentralized end-to-end, semi-decentralized end-to-end, and distributed hop-by-hop control approaches, our proposed congestion control strategies are investigated for a DiffServ loopless mesh network (Internet) and a DiffServ fully-connected NUS. Contrary to the semi-decentralized end-to-end congestion control strategy, in the distributed hop-by-hop congestion control strategy, each output port controller communicates the maximum allowed flow rate only to its immediate upstream node(s) and/or source(s). This approach reduces the required amount of information in the flow control when Compared to other approaches in which the allowed flow rate is sent to all the upstream sources communicating through an output port

    A formalism for describing and simulating systems with interacting components.

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    This thesis addresses the problem of descriptive complexity presented by systems involving a high number of interacting components. It investigates the evaluation measure of performability and its application to such systems. A new description and simulation language, ICE and it's application to performability modelling is presented. ICE (Interacting ComponEnts) is based upon an earlier description language which was first proposed for defining reliability problems. ICE is declarative in style and has a limited number of keywords. The ethos in the development of the language has been to provide an intuitive formalism with a powerful descriptive space. The full syntax of the language is presented with discussion as to its philosophy. The implementation of a discrete event simulator using an ICE interface is described, with use being made of examples to illustrate the functionality of the code and the semantics of the language. Random numbers are used to provide the required stochastic behaviour within the simulator. The behaviour of an industry standard generator within the simulator and different methods of number allocation are shown. A new generator is proposed that is a development of a fast hardware shift register generator and is demonstrated to possess good statistical properties and operational speed. For the purpose of providing a rigorous description of the language and clarification of its semantics, a computational model is developed using the formalism of extended coloured Petri nets. This model also gives an indication of the language's descriptive power relative to that of a recognised and well developed technique. Some recognised temporal and structural problems of system event modelling are identified. and ICE solutions given. The growing research area of ATM communication networks is introduced and a sophisticated top down model of an ATM switch presented. This model is simulated and interesting results are given. A generic ICE framework for performability modelling is developed and demonstrated. This is considered as a positive contribution to the general field of performability research

    On packet switch design

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    Novel techniques in large scaleable ATM switches

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    Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis
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