Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design

Design of an electric drivetrain for the Formula Student-class vehicle

Hlavním úkolem této diplomové práce bylo navrhnout a postavit funkční prototyp frekvenčního měniče pro použití ve vozidlech týmu eForce FEE Prague Formula, soutěžícího v mezinárodní inženýrské soutěži Formula Student. Práce je členěna do několika kapitol, kdy je nejdříve prozkoumán již minule provedený vývoj v týmu. Dále je vystavěna potřebná teorie pro vývoj frekvenčního měniče. Další kapitola detailně popisuje provedený vývoj zařízení. Poslední kapitoly se věnují zhodnocení navrženého měniče. Diplomová práce také prozkoumala nové možnosti v měření fázových proudů, umožňující vysokou přesnost při zachování nízké ceny a kompaktních rozměrů. Celkovým cílem bylo navrhnout jednoduché a robustní zařízení s nízkou výrobní cenou. Ověřování návrhu bylo provedeno v laboratořích fakulty pro ujištění připravenosti navrženého měniče pro nasazení do vozidla. Práce bude pokračovat na vylepšování řídícího algoritmu a postupné integraci do týmových vozidel.This thesis' main objective was to design and develop a functional motor controller for usage in a Formula Student competition vehicle of the eForce FEE Prague Formula team. Work is split into several chapters. Exploring a drivetrain development progression in the team, presenting a needed theory for a motor controller development and giving a detailed overview of the designed device. The last chapters are dedicated to evaluation of the design. Thesis had explored a new methodology in a phase current sensing, providing a significant precision while allowing for a low cost and compact design. Overall aim was to create a simple, robust and cheap solution. Verification of the design was performed in the laboratory environment of the faculty in order to ensure preparedness for integration into the vehicle. Further work will focus on control strategy improvements and final integration into the team's vehicles

Hardware design of a portable medical device to measure the quadriceps muscle group after a total knee arthroplasty by EMG, LBIA and clinical score methods

El propòsit d'aquest projecte és el disseny del hardware d'un dispositiu mèdic portàtil per a mesurar senyals d'electromiografia (EMG) i bioimpedància localitzada (LBIA), que s'utilitzarà per avaluar la progressió de dues pròtesis de genoll (Medial-Pivot i Ultra- Congruent) en pacients operats d'una artroplàstia total de genoll per a l'hospital Germans Trias i Pujol de Badalona. Per això, s'ha realitzat un estudi complet sobre els senyals d'EMG i LBIA, per tal de definir les característiques necessàries de l'equip mèdic i poder optimitzar el disseny electrònic. Per l'adquisició de senyals EMG, s'ha dissenyat i simulat un sistema compost per diferents fases, que treballen independentment per adquirir, amplificar, filtrar i adaptar el senyal EMG pel seu futur processament digital. D'altra banda, per obtenir valors de la bioimpedància localitzada dels diferents músculs que conformen el quàdriceps, s'ha dissenyat un sistema compost per dos grans blocs; el primer bloc és l'etapa d'injecció, on es genera i s'injecta un senyal feble de corrent altern a la zona a mesurar, mentre que el segon bloc, és l'etapa d'adquisició de senyals. Aquest últim s'encarrega d'adquirir la diferència de voltatge produïda per la injecció de corrent al múscul (anteriorment mencionat) per després calcular la bioimpedància a partir de la llei d'ohm. Tots els senyals són digitalitzats mitjançant el microcontrolador STM32F407VG, que s'encarregarà de processar i aconseguir les dades claus per determinar quina de les deus pròtesis desenvolupa una millor funció mecànica i una millor adaptació biològica. És important remarcar que tot el disseny, sigui per a EMG o LBIA s'ha dut a terme de manera discreta sense fer servir Front-Ends comercials o integrats complexos més que l'amplificador d'instrumentació o ADC. En addició, el present treball inclou una primera estimació dels costos de producció i fabricació per a una sola unitat, càlculs de consums i funcionament (sorolls, CMRR del sistema i amplada de banda) i una simulació completa d'EMG i LBIA per observar com funciona i es du a terme cada etapa del circuit. Finalment, en tractar-se d'un equip mèdic, també s'ha revisat la normativa aplicable i se n'ha analitzat l'impacte ambiental, s'ha proposat i definit diferents punts per a futurs treballs, com podria ser la validació i testatge de l'equip, càlculs més aproximats de consums i perfilar la bill of materials (BOM) per a grans demandes de components.The purpose of this project is the hardware design of a portable medical device to measure electromyography (EMG) and localized bioimpedance (LBIA) signals, which will be used to evaluate the adaptability and progression of two knee prostheses (medial-pivot and ultra-congruent) in patients undergoing total knee arthroplasty at the Germans Trias i Pujol Hospital in Badalona. For this, the present work undercovers the relevant properties of the EMG and LBIA signals in order to define the characteristics of the medical equipment and thus optimize its electronic design. For the EMG measurements, a system made up of different stages has been designed and simulated. These phases work independently to acquire, amplify, filter, and adapt the EMG signal for its further digital processing. On the other hand, to obtain the bioimpedance values of different quadriceps muscles, a system composed of two large blocks has been designed; the first is the injection block, where a weak alternating current signal is generated and injected into the area to be measured, while the second block is the signal acquisition stage. The purpose of the latter is to acquire the voltage difference produced by the injection of current (mentioned above) and then obtain the bioimpedance from Ohm's law. All the signals are digitized from the STM32F407VG microcontroller, which will be in charge of processing and obtaining the key data to determine which of the two prostheses performs a better mechanical function and biological adaptation. It is important to note that the entire design, whether for EMG or LBIA, has been developed discreetly without using commercial Front-Ends or complex ICs other than the instrumentation amplifier or ADC. In addition, the thesis includes a first estimation of the production and manufacturing costs for a single unit, calculations of consumption and work operation (noise, CMRR of the system and bandwidth) and a complete simulation of EMG and LBIA to observe how it works on each stage for both circuits. Finally, as it is a medical device, the applicable regulations have also been reviewed and its environmental impact has been analysed. Additionally, different points have been proposed and defined for future work, such as the construction of the PCB and its respective validation, improving both the consumption calculations and the list of materials (BOM) for large component demands.El propósito de este proyecto es el diseño del Hardware de un dispositivo médico portátil para mediciones de electromiografía (EMG) y bioimpedancia localizada (LBIA), que se utilizará para estudiar la evolución de la adaptabilidad y funcionamiento de dos prótesis de rodilla (medial-pívot y ultracongruente) en pacientes operados de artroplastia total de rodilla en el Hospital Germans Trias i Pujol de Badalona. Para ello, se ha realizado un estudio exhaustivo sobre las propiedades de las señales de EMG y LBIA con la finalidad de definir las características del equipo médico y de esta forma, optimizar el diseño electrónico del mismo. Para la lectura de mediciones EMG, se ha diseñado y simulado un sistema constituido por distintas etapas, que trabajan independientemente para adquirir, amplificar, filtrar, y adaptarla señal EMG para su posterior procesado digital. Por otro lado, para obtener los valores de bioimpedancia de distintos músculos del cuádriceps, se ha diseñado un sistema compuesto por dos grandes bloques; el primero es el bloque de inyección, donde se genera y se inyecta una señal débil de corriente alterna en la zona a medir, mientras que el segundo bloque es la etapa de adquisición de señales. Esta última tiene como finalidad adquirir la diferencia de voltaje producido por la inyección de corriente (anteriormente mencionada) para después obtener la bioimpedancia a partir de la ley de ohm. Todas las señales son digitalizadas a partir del microcontrolador STM32F407VG, que se encargará de procesar y obtener los datos claves para determinar cuál de las dos prótesis desempeña una mejor función mecánica y adaptación biológica. Es importante remarcar que todo el diseño, ya sea para EMG o LBIA, se ha desarrollado de manera discreta sin usar Front-Ends comerciales o integrados complejos más que el amplificador de instrumentación o ADC. En adición, la tesis incluye una primera estimación de los costes de producción y fabricación para una sola unidad, cálculos de consumos y funcionamiento (ruidos, CMRR del sistema y ancho de banda) y una simulación completa de EMG y LBIA para observar cómo funciona y se desarrolla cada etapa de los distintos circuitos. Finalmente, al tratarse de un equipo médico, también se ha revisado la normativa aplicable y se ha analizado el impacto ambiental del mismo. Por último, se han propuesto y definido distintos puntos para futuros trabajos, como es la construcción de la PCB y su respectiva validación, realizar cálculos más aproximados de consumos y perfilar la lista de materiales (BOM) para grandes demandas de componentes

Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

Ultra-fast Alternating Current Potential Drop Measurement System for Materials Characterization and Precision Impedance Analyzer for Eddy Current Measurement

The alternating current potential drop method (ACPD) with four-point probe injects alternating current into the sample under test from the two outer drive pins and measures the voltage (potential) drop between the two inner pick-pins. This method can be used to measure electrical conductivity, linear permeability, coating depth, as well as crack size. However, the measurement speed and accuracy of present ACPD system need to be dramatically improved. This work discusses the design, implementation and test of a novel ultra-fast standalone ACPD system. New and powerful hardware including high current transconductance amplifier and low noise amplifier provide a sound foundation for nearly perfect system level noise performance; new time domain to frequency domain conversion method increases the measurement speed without sacrificing noise performance. A general purpose calibration method is introduced so that the accuracy of this system is guaranteed. With the development and introduction of this new ACPD instrument, ACPD method has evolved from a laboratory NDE method to a full blown technique that is ready for real world application. The last chapter of this thesis discusses a simple but powerful lock-in amplifier based precision impedance analyzer. This impedance analyzer provides an economical solution to eddy current testing that requires highest precision

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

A Flexible, Highly Integrated, Low Power pH Readout

Medical devices are widely employed in everyday life as wearable and implantable technologies make more and more technological breakthroughs. Implantable biosensors can be implanted into the human body for monitoring of relevant physiological parameters, such as pH value, glucose, lactate, CO2 [carbon dioxide], etc. For these applications the implantable unit needs a whole functional set of blocks such as micro- or nano-sensors, sensor signal processing and data generation units, wireless data transmitters etc., which require a well-designed implantable unit.Microelectronics technology with biosensors has caused more and more interest from both academic and industrial areas. With the advancement of microelectronics and microfabrication, it makes possible to fabricate a complete solution on an integrated chip with miniaturized size and low power consumption.This work presents a monolithic pH measurement system with power conditioning system for supply power derived from harvested energy. The proposed system includes a low-power, high linearity pH readout circuits with wide pH values (0-14) and a power conditioning unit based on low drop-out (LDO) voltage regulator. The readout circuit provides square-wave output with frequency being highly linear corresponding to the input pH values. To overcome the process variations, a simple calibration method is employed in the design which makes the output frequency stay constant over process, supply voltage and temperature variations. The prototype circuit is designed and fabricated in a standard 0.13-μm [micro-meter] CMOS process and shows good linearity to cover the entire pH value range from 0-14 while the voltage regulator provides a stable supply voltage for the system

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

A Silicon Carbide Linear Voltage Regulator for High Temperature Applications

Current market demands have pushed the capabilities of silicon to the edge. High temperature and high power applications require a semiconductor device to operate reliably in very harsh environments. This situation has awakened interests in other types of semiconductors, usually with a higher bandgap than silicon\u27s, as the next venue for the fabrication of integrated circuits (IC) and power devices. Silicon Carbide (SiC) has so far proven to be one of the best options in the power devices field. This dissertation presents the first attempt to fabricate a SiC linear voltage regulator. This circuit would provide a power management option for developing SiC processes due to its relatively simple implementation and yet, a performance acceptable to today\u27s systems applications. This document details the challenges faced and methods needed to design and fabricate the circuit as well as measured data corroborating design simulation results

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio