NoC emulation: a tool and design flow for MPSoC

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing; thus, the amount of processors, memories and application-specific signal pro- cessing cores is rapidly increasing. In these new Multi- Processor SoCs, (MPSoCs) one of the most critical elements regarding overall efficiency is on-chip interconnections. Network-On-Chip(NoC) provides a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or ad hoc topologies and can be tuned by a large set of parameters. Simulation and functional validation are essential to assess the correctness and performance of MPSoC architectures. We present a flexible hardware-software emulation framework implemented on an FPGA that is specially designed to suitably explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy and flexibility of software simulators. Finally, we propose a validation flow for MPSoCs based on our flexible NoC emulation framework, which allows designers to explore and optimize a range of solutions, as well as quickly characterize performance figures and identify possible limitations in their on-chip interconnection architectures

A template router

Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine these approaches. However, a new type of router is required for such a combination; namely, the template router. This paper presents a template router and discusses how routing is coded and how this code is generated using the well known A* Algorithm.Peer Reviewe