A Hierachical Infrastrucutre for SOC Test Management

HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

CAS-BUS: A scalable and reconfigurable test access mechanism for systems on a chip

This paper describes CAS-BUS, a P1500 compatible Test Access Mechanism for Systems on a Chip. The TAM architecture is made up of a Core Access Switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper

A test architecture design for SoCs using ATAM method

Test arranging is a basic issue in structure on-a-chip (S.O.C) experiment mechanization. Capable investigation designs constrain the general organization check request time, keep away from analysis reserve conflicts, in addition to purpose of restriction control disseminating in the midst of examination manner. In this broadsheet, we absent a fused method to manage a couple of test arranging issues. We first present a system to choose perfect timetables for sensibly evaluated SOC’s among need associations, i.e., plans that spare alluring orderings among tests. This furthermore acquaints a capable heuristic estimation with plan examinations designed for enormous S.O.Cs through need necessities in polynomial occasion. We portray a narrative figuring with the purpose of uses pre-emption of tests to secure capable date-books in favour of SOCs. Exploratory marks on behalf of an educational S-O-C plus a cutting edge SOC exhibit with the aim of capable investigation timetables be able to subsist gained in sensible CPU occasion

SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper

HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs

Proposes HD2BIST, a complete hierarchical framework for BIST scheduling, data patterns delivering, and diagnosis of a complex system including embedded cores with different test requirements as full scan cores, partial scan cores, or BIST-ready cores. The main goal of HD2BIST is to maximize and simplify the reuse of the built-in test architectures, giving the chip designer the highest flexibility in planning the overall SoC test strategy. HD2BIST defines a test access method able to provide a direct “virtual” access to each core of the system, and can be conceptually considered as a powerful complement to the P1500 standard, whose main target is to make the test interface of each core independent from the vendo

A Case Study of Hierarchical Diagnosis for Core-Based SoC

In this paper, a silicon debug case study was given in the context of a hierarchical diagnosis flow for core-based SoC. We discuss (1) how to design a simple core wrapper that supports at-speed test, (2) how to map the failures collected from the chip level to core level, and (3) how to perform failure analysis and silicon debug under the guidance of diagnosis results. Terminology and Introduction The terminology used in this paper is briefly discussed below. SoC: Designs that integrate a complete system onto one chip are called System-on-a-Chip (SoC) designs. Core: In SoC designs, the design process involves an IC that is often made up of large pre-defined and preverified reusable building blocks or intellectual property (IP) blocks, such as digital logic, processors, memories, analog and mixed signal circuits. The IC building blocks are called cores or embedded cores Core Wrapper Design The IEEE 1500 core wrapper [8] is illustrated in (1) Wrapper Serial Port (WSP) has a set of serial terminals that could be sourced from chip-level pins or from an embedded controller such as an IEEE 1149.1-based (JTAG) controller. The WSP is used to load and unload instructions and data into and out of the IEEE 1500 registers. In addition to the wrapper serial input (WSI) and wrapper serial output (WSO) terminals shown i