Experimental Test bed to De-Risk the Navy Advanced Development Model

This paper presents a reduced scale demonstration test-bed at the University of Texas’ Center for Electromechanics (UT-CEM) which is well equipped to support the development and assessment of the anticipated Navy Advanced Development Model (ADM). The subscale ADM test bed builds on collaborative power management experiments conducted as part of the Swampworks Program under the US/UK Project Arrangement as well as non-military applications. The system includes the required variety of sources, loads, and controllers as well as an Opal-RT digital simulator. The test bed architecture is described and the range of investigations that can be carried out on it is highlighted; results of preliminary system simulations and some initial tests are also provided. Subscale ADM experiments conducted on the UT-CEM microgrid can be an important step in the realization of a full-voltage, full-power ADM three-zone demonstrator, providing a test-bed for components, subsystems, controls, and the overall performance of the Medium Voltage Direct Current (MVDC) ship architecture.Center for Electromechanic

A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

Integrated circuit interface for artificial skins

Artificial sensitive skins are intended to emulate the human skin to improve the skills of robots and machinery in complex unstructured environments. They are basically smart arrays of pressure sensors. As in the case of artificial retinas, one problem to solve is the management of the huge amount of information that such arrays provide, especially if this information should be used by a central processing unit to implement some control algorithms. An approach to manage such information is to increment the signal processing performed close to the sensor in order to extract the useful information and reduce the errors caused by long wires. This paper proposes the use of voltage to frequency converters to implement a quite straightforward analog to digital conversion as front end interface to digital circuitry in a smart tactile sensor. The circuitry commonly implemented to read out the information from a piezoresistive tactile sensor can be modified to turn it into an array of voltage to frequency converters. This is carried out in this paper, where the feasibility of the idea is shown through simulations and its performance is discussed.Gobierno de España TEC2006-12376-C02-01, TEC2006-1572

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

Advanced sensors technology survey

This project assesses the state-of-the-art in advanced or 'smart' sensors technology for NASA Life Sciences research applications with an emphasis on those sensors with potential applications on the space station freedom (SSF). The objectives are: (1) to conduct literature reviews on relevant advanced sensor technology; (2) to interview various scientists and engineers in industry, academia, and government who are knowledgeable on this topic; (3) to provide viewpoints and opinions regarding the potential applications of this technology on the SSF; and (4) to provide summary charts of relevant technologies and centers where these technologies are being developed

Design enhancements of the smart sediment particle for riverbed transport monitoring

This paper discusses new enhancements that are being made to the existing ‘Smart Sediment Particle’. The smart sediment particle has been designed and implemented to track its own 3-dimensional trajectory when placed in a riverbed. This device serves as a tool to detect sedimentation in rivers. The device has been developed over the years, with its size diminishing significantly down to a sphere of 2cm radius. The readings obtained from the pebble are accurate and match well with other independent motion sensor readings. Currently a novel IPT (Inductive Power Transfer) based power supply is being integrated to this device, to charge it wirelessly, when it has been extracted from the water. A new low power, miniaturized microcontroller has been introduced to minimize the power consumption and the PCB real estate of the device. The paper discusses these new enhancements in detail and also other potential enhancements such as error compensation and wireless data transfer

Design Of Neural Network Circuit Inside High Speed Camera Using Analog CMOS 0.35 ¼m Technology

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs , readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network

Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them.This work has been partially funded by the Spanish Government under contracts TEC2006-12376 and TEC2009-14446

Development and optimization of zeolite synthesis route from natural koalin for adsorption of dyes

Synthesis of zeolite using kaolin as the main source of alumina and silica has been identified as a novel zeolite production process, which could reduce the cost of using the synthetic reagents and the high energy consumption. A low grade kaolin was used for studying the most suitable synthesis route and operating parameters for producing a high yield and pure phase zeolite. The study adopted the alkaline activation and microwave assisted heating as modification techniques of the conventional hydrothermal synthesis process. Calcination and crystallization proceses were identified as the bottleneck operations within the process. Hence, this study employed 2k factorial design of experiment to study the relationship of metakaolinization temperature of 600 – 800 oC with calcination time of 1 – 5 hours. And that of crystallization time of 9 – 16 hours with aging treatment time of 12 – 36 hours. Central Composite Design (CCD) is used for optimization with axial and center point for factors evaluation towards the responses; yield percent (%) and crystallinity (%) for crystallization process. Based on the Response Surface Methodology (RSM), with desirability value of 98.67 %, the significant parametric aging condition is 27 hours and crystallization time is 9 hours were suggested to yield an optimum product for 80.47 yield percent and 76.92 crystallinity. Three confirmation runs were performed based on the suggested optimum parameter and the calculated error value was found to be below 10 %. The synthesized zeolite-A from the confirmation runs was characterized through XRD. The results were then corroborated with the analytical results from SEM, BET and FTIR. The activity of the synthesized zeolite A was confirmed by a structural refinement analysis, that identified the product as a member of the cubic crystalline systems, belonging to a Fm3c space group with lattice cubic structure values where