Demonstration of sustained and useful converter responses during balanced and unbalanced faults in microgrids

In large power grids where converter penetration is presently low and the network impedance is predominantly reactive, the required response from converters during faults is presently specified by phrases such as “maximum reactive output”. However, in marine and aero power systems most faults are unbalanced, the network impedance is resistive, and converter penetration may be high. Therefore a balanced reactive fault current response to an unbalanced fault may lead to over-voltages or over/under frequency events. Instead, this paper presents a method of controlling the converter as a balanced voltage source behind a reactance, thereby emulating the fault response of a synchronous generator (SG) as closely as possible. In this mode there is a risk of converter destruction due to overcurrent. A new way of preventing destruction but still providing fault performance as close to a SG as possible is presented. Demonstrations are presented of simulations and laboratory testing at the 10kVA 400V scale, with balanced and unbalanced faults. Currents can be limited to about 1.5pu while still providing appropriate unbalanced fault response within a resistive network

SIDO Buck converter with independent outputs

The portable electronics market is rapidly migrating towards more compact devices requiring multiple high-integrity high-efficiency voltage supplies for empowering the systems. This paper demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3V. The main target is low cross regulation between the two outputs to supply independent load current levels while maintaining desired output voltage values well within a ripple that is set by adaptive hysteresis levels. A reverse current detector to avoid negative current flowing through the inductor prevents efficiency degradation at light load.Postprint (published version

SIDO Buck converter with independent outputs

The portable electronics market is rapidly migrating towards more compact devices requiring multiple high-integrity high-efficiency voltage supplies for empowering the systems. This paper demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3V. The main target is low cross regulation between the two outputs to supply independent load current levels while maintaining desired output voltage values well within a ripple that is set by adaptive hysteresis levels. A reverse current detector to avoid negative current flowing through the inductor prevents efficiency degradation at light load.Postprint (published version

On-chip SIDO buck converter with independent outputs

The portable electronics market is rapidly migrating towards more compact devices requiring multiple high-integrity high-efficiency voltage supplies for empowering the systems. This paper demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3 V. The main targets are low cross regulation between the two outputs to supply independent load current levels while maintaining desired output voltage values well within the acceptable ripple levels. The proposed controller provides adaptive levels in order to limit the output ripple, achieving a high output voltage accuracy. A reverse current detector to avoid negative current flowing through the inductor, prevents possible efficiency degradation.Postprint (published version

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Polynomial Curve Slope Compensation for Peak-Current-Mode-Controlled Power Converters

Linear ramp slope compensation (LRC) and quadratic slope compensation (QSC) are commonly implemented in peak-current-mode-controlled dc-dc converters in order to minimize subharmonic and chaotic oscillations. Both compensating schemes rely on the linearized state-space averaged model (LSSA) of the converter. The LSSA ignores the impact that switching actions have on the stability of converters. In order to include switching events, the nonlinear analysis method based on the Monodromy matrix was introduced to describe a complete-cycle stability. Analyses on analog-controlled dc-dc converters applying this method show that system stability is strongly dependent on the change of the derivative of the slope at the time of switching instant. However, in a mixed-signal-controlled system, the digitalization effect contributes differently to system stability. This paper shows a full complete-cycle stability analysis using this nonlinear analysis method, which is applied to a mixed-signal-controlled converter. Through this analysis, a generalized equation is derived that reveals for the first time the real boundary stability limits for LRC and QSC. Furthermore, this generalized equation allows the design of a new compensating scheme, which is able to increase system stability. The proposed scheme is called polynomial curve slope compensation (PCSC) and it is demonstrated that PCSC increases the stable margin by 30% compared to LRC and 20% to QSC. This outcome is proved experimentally by using an interleaved dc-dc converter that is built for this work

Low-to-Medium Power Single Chip Digital Controlled DC-DC Regulator for Point-of-Load Applications

A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal

Frequency-modulation control of a DC/DC current-source parallel-resonant converter

This paper proposes a frequency-modulation control scheme for a dc/dc current-source parallel-resonant converter with two possible configurations. The basic configuration comprises an external voltage loop, an internal current loop, and a frequency modulator: the voltage loop is responsible for regulating the output voltage, the current loop makes the system controllable and limits the input current, and the modulator provides robustness against variations in resonant component values. The enhanced configuration introduces the output inductor current as a feed-forward term and clearly improves the transient response to fast load changes. The theoretical design of these control schemes is performed systematically by first deriving their small-signal models and second using Bode diagram analysis. The actual performance of the proposed control schemes is experimentally validated by testing on a laboratory prototype.Peer ReviewedPostprint (author's final draft