Allocation of geometric tolerances in one-dimensional stackup problems

Many tolerancing problems on mechanical assemblies involve a functional requirement depending on a chain of parallel dimensions on individual parts. In these one-dimensional cases, simple methods are available for the analysis and the allocation of dimensional tolerances. However, they are difficult to extend to geometric tolerances, which must be translated into equivalent dimensional tolerances; this allows the analysis but makes the allocation generally impossible without Monte Carlo simulation and complex search strategies. To overcome this difficulty, the paper proposes a way of dealing directly with geometric tolerances in the allocation problem. This consists in expressing the functional requirement as a linear model of geometric tolerances rather than equivalent dimensional tolerances; the coefficients of the model (sensitivities) are calculated considering both the dimension chain and the standard definition of the geometric tolerances. The approach can be combined with any constrained optimization method based on sensitivities. The optimal scaling method, previously proposed for dimensional tolerances, is extended to geometric tolerances and used in two examples to demonstrate the simplicity of the overall workflow and the quality of the optimal solution

Sensitivity analysis applied to computer-aided circuit design

Imperial Users onl

Self-resilient production systems : framework for design synthesis of multi-station assembly systems

Product design changes are inevitable in the current trend of time-based competition where product models such as automotive bodies and aircraft fuselages are frequently upgraded and cause assembly process design changes. In recent years, several studies in engineering change management and reconfigurable systems have been conducted to address the challenges of frequent product and process design changes. However, the results of these studies are limited in their applications due to shortcomings in three aspects which are: (i) They rely heavily on past records which might only be a few relevant cases and insufficient to perform a reliable analysis; (ii) They focus mainly on managing design changes in product architecture instead of both product and process architecture; and (iii) They consider design changes at a station-level instead of a multistation level. To address the aforementioned challenges, this thesis proposes three interrelated research areas to simulate the design adjustments of the existing process architecture. These research areas involve: (i) the methodologies to model the existing process architecture design in order to use the developed models as assembly response functions for assessing Key Performance Indices (KPIs); (ii) the KPIs to assess quality, cost, and design complexity of the existing process architecture design which are used when making decisions to change the existing process architecture design; and (iii) the methodology to change the process architecture design to new optimal design solutions at a multi-station level. In the first research area, the methodology in modeling the functional dependence of process variables within the process architecture design are presented as well as the relations from process variables and product architecture design. To understand the engineering change propagation chain among process variables within the process architecture design, a functional dependence model is introduced to represent the design dependency among process variables by cascading relationships from customer requirements, product architecture, process architecture, and design tasks to optimise process variable design. This model is used to estimate the level of process variable design change propagation in the existing process architecture design Next, process yield, cost, and complexity indices are introduced and used as KPIs in this thesis to measure product quality, cost in changing the current process design, and dependency of process variables (i.e, change propagation), respectively. The process yield and complexity indices are obtained by using the Stream-of-Variation (SOVA) model and functional dependence model, respectively. The costing KPI is obtained by determining the cost in optimizing tolerances of process variables. The implication of the costing KPI on the overall cost in changing process architecture design is also discussed. These three comprehensive indices are used to support decision-making when redesigning the existing process architecture. Finally, the framework driven by functional optimisation is proposed to adjust the existing process architecture to meet the engineering change requirements. The framework provides a platform to integrate and analyze several individual design synthesis tasks which are necessary to optimise the multi-stage assembly processes such as tolerance of process variables, fixture layouts, or part-to-part joints. The developed framework based on transversal of hypergraph and task connectivity matrix which lead to the optimal sequence of these design tasks. In order to enhance visibility on the dependencies and hierarchy of design tasks, Design Structure Matrix and Task Flow Chain are also adopted. Three scenarios of engineering changes in industrial automotive design are used to illustrate the application of the proposed redesign methodology. The thesis concludes that it is not necessary to optimise all functional designs of process variables to accommodate the engineering changes. The selection of only relevant functional designs is sufficient, but the design optimisation of the process variables has to be conducted at the system level with consideration of dependency between selected functional designs

Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano

Design of microwave filters and multiplexers in waveguide technology using distributed models

This thesis introduces new design techniques for microwave filters and multiplexers in waveguide technology. These devices find wide application in communication systems, such as satellite links or wireless base stations. In particular, the work has been focused in the design of circular-waveguide dualmode (CWDM) filters. The synthesis technique makes use of distributed models, which are a halfway point between the fast but imprecise lumped circuit models, and the more accurate but costly full-wave electromagnetic models. An automatic software tool to design this type of filters has also been developed, which is able to obtain the physical dimensions of the filter in a matter of minutes. A new technique to correct manufacturing deviations in CWDM filters is proposed next, which avoids the use of tuning screws. Instead, fixed squared insertions are employed, which can be fabricated in separated pieces. An space mapping technique is used to calculate the dimensions of these pieces and, after few iterations, the procedure is able to achieve the required response. A systematic method to design manifold-coupled multiplexers is also presented, which also employs distributed models. First, the design of classic multiplexers with CWDM filters is considered. The whole design procedure is thoroughly explained, starting from the required specifications and finishing with the physical dimensions. Finally, the design of a non-conventional wideband multiplexer with a new type of rectangular-waveguide filters is addressed.Brumos Vicente, M. (2014). Design of microwave filters and multiplexers in waveguide technology using distributed models [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/48492TESI

Optimal fault-tolerant flight control for aircraft with actuation impairments

Current trends towards greater complexity and automation are leaving modern technological systems increasingly vulnerable to faults. Without proper action, a minor error may lead to devastating consequences. In flight control, where the controllability and dynamic stability of the aircraft primarily rely on the control surfaces and engine thrust, faults in these effectors result in a higher extent of risk for these aspects. Moreover, the operation of automatic flight control would be suddenly disturbed. To address this problem, different methodologies of designing optimal flight controllers are presented in this thesis. For multiple-input multiple-output (MIMO) systems, the feedback optimal control is a prominent technique that solves a multi-objective cost function, which includes, for instance, tracking requirements and control energy minimisation. The first proposed method is based on a linear quadratic regulator (LQR) control law augmented with a fault-compensation scheme. This fault-tolerant system handles the situation in an adaptive way by solving the optimisation cost function and considering fault information, while assuming an effective fault detection system is available. The developed scheme was tested in a six-degrees-of-freedom nonlinear environment to validate the linear-based controller. Results showed that this fault tolerant control (FTC) strategy managed to handle high magnitudes of the actuator’s loss of effciency faults. Although the rise time of aircraft response became slower, overshoot and settling errors were minimised, and the stability of the aircraft was maintained. Another FTC approach has been developed utilising the features of controller robustness against the system parametric uncertainties, without the need for reconfiguration or adaptation. Two types of control laws were established under this scheme, the H∞ and µ-synthesis controllers. Both were tested in a nonlinear environment for three points in the flight envelope: ascending, cruising, and descending. The H∞ controller maintained the requirements in the intact case; while in fault, it yielded non-robust high-frequency control surface deflections. The µ-synthesis, on the other hand, managed to handle the constraints of the system and accommodate faults reaching 30% loss of effciency in actuation. The final approach is based on the control allocation technique. It considers the tracking requirements and the constraints of the actuators in the design process. To accommodate lock-in-place faults, a new control effort redistribution scheme was proposed using the fuzzy logic technique, assuming faults are provided by a fault detection system. The results of simulation testing on a Boeing 747 multi-effector model showed that the system managed to handle these faults and maintain good tracking and stability performance, with some acceptable degradation in particular fault scenarios. The limitations of the controller to handle a high degree of faults were also presented

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures