Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified

Circuit Techniques for Multiple and Wideband Beamforming

University of Minnesota Ph.D. dissertation.June 2018. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); x, 102 pages.This thesis presents different architectures with regard to multiple beamforming and wideband phased array transceiver. Three different designs are implemented in TSMC 65nm RF CMOS to demonstrate different solutions. The design in this thesis have included major RF blocks in state-of-art wireless transceiver: RF receiver, local oscillator, and RF transmitter. First, a RF/analog FFT based four-channel four-beam receiver with progressive partial spatial ltering is proposed. This architecture is particularly well suited for MIMO systems where multiple beams are used to increase throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial ltering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial ltering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0:65mm2 excluding pads and test circuits. Second, a wideband phased array receiver architecture with simultaneous spectral and spatial filtering by sub-harmonic injection oscillators is presented. The design avoids using expensive delay elements by many conventional wideband phased array. Different from prior art of channelization which cannot solve beam-squinting issue among the sub-channels, we use sub-harmonic injection locking scheme, which make the center frequencies of all sub-channels point to the same spatial direction to overcome beam-squinting issue. The low frequency, low power and narrowband phase shifters are placed at LO in comparison to conventional way of placing delay elements or phase shifters in the signal path. This avoids receiver performance degradation from delay elements or phase shifters. The simultaneous spectral and spatial ltering dictates less ADC dynamic range requirement and further reduces power. The injection locking scheme reduces the phase noise contribution from the oscillators. The two-band prototype design realized in 65nm GP CMOS is centered at 9GHz, provides 4GHz instantaneous bandwidth, reduces beam-squinting by half, consumes 31.75mW/antenna and occupies 2.7mm2 of chip area. In the third work, a steerable RF/analog FFT based four-beam transmitter architecture is presented. This work is based on the idea of FFT based multiple beamforming in 1st work, but extended to the transmitter and make the all beams steerable. Due to the reciprocity between receiver and transmitter, decimation-in-frequency (DIF) FFT is utilized in the transmitter. All the beams are steered simultaneously by front-end phase shifters, while keep each of the beams is independent of the others. The steerability of FFT based multiple beamforming scheme makes this proposed prototype could tackle more complicated portable wireless environment. The first and second proposed architecture have been silicon veried, and the design of the third has been finished and ready for tapeout

Digital and Mixed Domain Hardware Reduction Algorithms and Implementations for Massive MIMO

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity. Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for elements. The number of ADCs is the key deterministic factor for the power consumption of an antenna array system. The digital hardware consists of fast Fourier transform (FFT) cores with a multiplier complexity of (N log2N) for an element system to generate multiple beams. It is required to reduce the mixed and digital hardware complexities in MIMO systems to reduce the cost and the power consumption, while maintaining high performance. The well-known concept has been in use for ADCs to achieve reduced complexities. An extension of the architecture to multi-dimensional domain is explored in this dissertation to implement a single port ADC to replace ADCs in an element system, using the correlation of received signals in the spatial domain. This concept has applications in conventional uniform linear arrays (ULAs) as well as in focal plane array (FPA) receivers. Our analysis has shown that sparsity in the spatio-temporal frequency domain can be exploited to reduce the number of ADCs from N to where . By using the limited field of view of practical antennas, multiple sub-arrays are combined without interferences to achieve a factor of K increment in the information carrying capacity of the ADC systems. Applications of this concept include ULAs and rectangular array systems. Experimental verifications were done for a element, 1.8 - 2.1 GHz wideband array system to sample using ADCs. This dissertation proposes that frequency division multiplexing (FDM) receiver outputs at an intermediate frequency (IF) can pack multiple (M) narrowband channels with a guard band to avoid interferences. The combined output is then sampled using a single wideband ADC and baseband channels are retrieved in the digital domain. Measurement results were obtained by employing a element, 28 GHz antenna array system to combine channels together to achieve a 75% reduction of ADC requirement. Implementation of FFT cores in the digital domain is not always exact because of the finite precision. Therefore, this dissertation explores the possibility of approximating the discrete Fourier transform (DFT) matrix to achieve reduced hardware complexities at an allowable cost of accuracy. A point approximate DFT (ADFT) core was implemented on digital hardware using radix-32 to achieve savings in cost, size, weight and power (C-SWaP) and synthesized for ASIC at 45-nm technology

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

RF and Millimeter-wave Techniques to Improve Scalability and Efficiency of Digital Beamforming Arrays

Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency bands. Chapter 3 presents a single wire IF interface design for phased array receivers which enables simple IF backhaul for high data volume MIMO systems. Finally a outphasing power amplifier(PA) design is presented in chapter 4 along with a driver amplifier with digital amplitude modulation to achieve state of the art power back off efficiency, which reduces battery usage and thus increases mobility. The first part of this thesis demonstrates the use of orthogonal sequences along to N-path filters to achieve reconfigurable select/reject filtering of signals based on their spatial, spectral and code-domain properties. A frequency/code-domain reject and select filtering is proposed and implemented using N-path switching with passive inductors as correlators. Using inductors instead of capacitors in N-path filters is challenging because of large inductance value required for our application demands use of off-chip inductors, which comes with associated parasitics and lower self-resonance frequency. In this design a cascaded inductor approach and differential N-path filtering is used to overcome inductor parasitics and enable operation at 1 GHz. A code-domain notch filter followed by a code-domain select receiver is designed and implemented in 65-nm CMOS technology. Measurements demonstrate 0.5 GHz to 1.0 GHz filter tuning range, with a maximum 26dB rejection for a blocker signal with 8dBm power, while consuming 60mW (at 1GHz operation frequency) and occupying 1.2mm2 of die area. Second part of this thesis demonstrates a single wire IF interface to simplify scaling of millimeter-wave(mm-Wave) phased array systems while preserving the data from each element, this enables spatial multiplexing, virtual arrays for radar, digital beamforming(DBF), etc. However, per-element digitization results in a formidable I/O challenge in large-scale tiled MIMO mm-Wave arrays. This dissertation demonstrates a 28 GHz 4-element MIMO RX with a single-wire interface that multiplexes the baseband signals of all elements and the LO reference through code-domain multiplexing. System considerations are presented and the approach is validated through DBF after de-multiplexing of the baseband signals from the single wire. Each element in the array achieves 16 dB conversion gain and ∼ 7 dB noise figure(NF) while consuming 60 mA from 1.2 V. The IC occupies 5.75 mm² in 65-nm CMOS. Final part of this thesis describes the design and implementation of a digital outphasing PA at 28 GHz to achieve state of the art back of efficiency. Outphasing PA require branch PA units to act as voltage sources(very low output impedance), which is challenging at mm-Wave frequencies. In this PA design an approximate class-F operation is achieved by tuning PA load network for up to 3rd harmonic. A stacked PA architecture is used for individual PA units to achieve high maximum power output. Output-power further improved by utilizing a novel diode connected stack bias circuit to improve out-put swing. PA delivers a maximum output-power of 20 dBm with a peak power added efficiency(PAE) of 27% (PA along with driver stages) and 6 dB back-off PAE of 16.5%

Array Architectures and Physical Layer Design for Millimeter-Wave Communications Beyond 5G

Ever increasing demands in mobile data rates have resulted in exploration of millimeter-wave (mmW) frequencies for the next generation (5G) wireless networks. Communications at mmW frequencies is presented with two keys challenges. Firstly, high propagation loss requires base stations (BSs) and user equipment (UEs) to use a large number of antennas and narrow beams to close the link with sufficient received signal power. Consequently, communications using narrow beams create a new challenge in channel estimation and link establishment based on fine angular probing. Current mmW system use analog phased arrays that can probe only one angle at the time which results in high latency during link establishment and channel tracking. It is desirable to design low latency beam training by exploring both physical layer designs and array architectures that could replace current 5G approaches and pave the way to the communications for frequency bands in higher mmW band and sub-THz region where larger antenna arrays and communications bandwidth can be exploited. To this end, we propose a novel signal processing techniques exploiting unique properties of mmW channel, and show both theoretically, in simulation and experiments its advantages over conventional approaches. Secondly, we explore different array architecture design and analyze their trade-offs between spectral efficiency and power consumption and area. For comprehensive comparison, we have developed a methodology for optimal design of system parameters for different array architecture candidates based on the spectral efficiency target, and use these parameters to estimate the array area and power consumption based on the circuits reported in the literature. We show that the hybrid analog and digital architectures have severe scalability concerns in radio frequency signal distribution with increased array size and spatial multiplexing levels, while the fully-digital array architectures have the best performance and power/area trade-offs.The developed approaches are based on a cross-disciplinary research that combines innovation in model based signal processing, machine learning, and radio hardware. This work is the first to apply compressive sensing (CS), a signal processing tool that exploits sparsity of mmW channel model, to accelerate beam training of mmW cellular system. The algorithm is designed to address practical issues including the requirement of cell discovery and synchronization that involves estimation of angular channel together with carrier frequency offset and timing offsets. We have analyzed the algorithm performance in the 5G compliant simulation and showed that an order of magnitude saving is achieved in initial access latency for the desired channel estimation accuracy. Moreover, we are the first to develop and implement a neural network assisted compressive beam alignment to deal with hardware impairments in mmW radios. We have used 60GHz mmW testbed to perform experiments and show that neural networks approach enhances alignment rate compared to CS. To further accelerate beam training, we proposed a novel frequency selective probing beams using the true-time-delay (TTD) analog array architecture. Our approach utilizes different subcarriers to scan different directions, and achieves a single-shot beam alignment, the fastest approach reported to date. Our comprehensive analysis of different array architectures and exploration of emerging architectures enabled us to develop an order of magnitude faster and energy efficient approaches for initial access and channel estimation in mmW systems