Capacitive Touch Panel with Low Sensitivity to Water Drop employing Mutual-coupling Electrical Field Shaping Technique

This paper proposes a novel method to reduce the water interference on the touch panel based on mutual-capacitance sensing in human finger detection. As the height of a finger (height >10 mm) is far larger than that of a water-drop (height 10 mm) and low in the low-height space (height <1 mm), the sensing cell can be designed to distinguish the finger from the water-drop. To achieve this density distribution of the electrical field, the mutual-coupling electrical field shaping (MEFS) technique is employed to build the sensing cell. The drawback of the MEFS sensing cell is large parasitic capacitance, which can be overcome by a readout IC with low sensitivity to parasitic capacitance. Experiments show that the output of the IC with the MEFS sensing cell is 1.11 V when the sensing cell is touched by the water-drop and 1.23 V when the sensing cell is touched by the finger, respectively. In contrast, the output of the IC with the traditional sensing cell is 1.32 and 1.33 V when the sensing cell is touched by the water-drop and the finger, respectively. This demonstrates that the MEFS sensing cell can better distinguish the finger from the water-drop than the traditional sensing cell does.National Research Foundation (NRF)Accepted versionThis work was supported in part by the National Natural Science Foundation of China (NSFC) under Grant 61771363, in part by the China Scholarship Council (CSC) under Grant 201706960042, and in part by the National Research Foundation of Singapore under Grant NRF-CRP11-2012-01

BiCMOS Power Detector for Pulsed RF Power Amplifiers

A BiCMOS power detector for pulsed radio-frequency power amplifiers is proposed. Given the pulse waveform and a fraction of the power amplifier’s input or output signal, the detector utilizes a low-frequency feedback loop to perform a successive approximation of the amplitude of the input signal. Upon completion of the successive approximation, the detector returns 9-bits representing the amplitude of the RF input signal. Using the pulse waveform from the power amplifier, the detector can dynamically adjust the rate of the binary search operation in order to return the updated amplitude information of the RF input signal at least every 1ms. The detector can handle pulse waveform frequencies from 50kHz to 10MHz with duty cycles in the range of 5 - 50% and peak power levels of -10 to 10dBm. The signal amplitude measurement can be converted to a peak power measurement accurate to within ±0.6dB of the input RF power

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

BiCMOS Power Detector for Pulsed RF Power Amplifiers

A BiCMOS power detector for pulsed radio-frequency power amplifiers is proposed. Given the pulse waveform and a fraction of the power amplifier’s input or output signal, the detector utilizes a low-frequency feedback loop to perform a successive approximation of the amplitude of the input signal. Upon completion of the successive approximation, the detector returns 9-bits representing the amplitude of the RF input signal. Using the pulse waveform from the power amplifier, the detector can dynamically adjust the rate of the binary search operation in order to return the updated amplitude information of the RF input signal at least every 1ms. The detector can handle pulse waveform frequencies from 50kHz to 10MHz with duty cycles in the range of 5 - 50% and peak power levels of -10 to 10dBm. The signal amplitude measurement can be converted to a peak power measurement accurate to within ±0.6dB of the input RF power

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514,S/s prototype (ReDAC1) and on a 11-bit, 10.5,kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68,LSB (1.53,LSB) maximum INL, 1.54,LSB (1.0,LSB) maximum DNL, 76.4,dB (67.9,dB) THD, 79.7,dB (71.4,dB) SFDR and 71.3,dB (63.3,dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB)