The 'gated-diode' configuration in MOSFET's, a sensitive tool for characterizing hot-carrier degradation

This paper describes a new measurement technique, the forward gated-diode current characterized at low drain voltages to be applied in MOSFET's for investigating hot-carrier stress-induced defects at high spatial resolution. The generation/recombination current in the drain-to-substrate diode as a function of gate voltage, combined with two-dimensional numerical simulation, provides a sensitive tool for detecting the spatial distribution and density of interface defects. In the case of strong accumulation, additional information is obtained from interband tunneling processes occurring via interface defects. The various mechanisms for generating interface defects and fixed charges at variable stress conditions are discussed, showing that information complementary to that available from other methods is obtaine

Influence of the spatial distribution of border traps in the capacitance frequency dispersion of Al2O3/InGaAs

In this paper, the capacitance frequency dispersion in strong accumulation of capacitance voltage curves has been studied for different high-k dielectric layers in MOS stacks. By studying experimental data at low (77 K) and room temperature (300 K), in oxides with different density of defects, it was possible reflect the spatial distribution of the defects in the capacitance frequency dispersion. The experimental data show that while at room temperature, the capacitance dispersion is dominated by the exchange of carriers from the semiconductor into oxide traps far away from the interface, at low temperature the oxide traps near the Al2O3/InGaAs interface are responsible for the frequency dispersion. The results indicate that the capacitance dispersion in strong accumulation reflect the spatial distribution of traps within the oxide, and that dielectric/semiconductor conduction band offset is a critical parameter for determining the capacitance dispersion for Al2O3/InGaAs based gate stacks.Fil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional; ArgentinaFil: Aguirre, Fernando Leonel. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Comisión Nacional de Energía Atómica; ArgentinaFil: Pazos, Sebastián Matías. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional; Argentina. Comisión Nacional de Energía Atómica; ArgentinaFil: Krylov, Igor. Technion - Israel Institute of Technology; IsraelFil: Winter, Roy. Technion - Israel Institute of Technology; IsraelFil: Eizenberg, Moshe. Technion - Israel Institute of Technology; Israe

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region

Interface Roughness Effects in Ultra-Thin Tunneling Oxides

Advanced MOSFET for ULSI and novel silicon-based devices require the use of ultrathin tunneling oxides where non-uniformity is often present. We report on our theoretical study of how tunneling properties of ultra-thin oxides are affected by roughness at the silicon/oxide interface. The effect of rough interfacial topography is accounted for by using the Planar Supercell Stack Method (PSSM) which can accurately and efficiently compute scattering properties of 3D supercell structures. Our results indicate that while interface roughness effects can be substantial in the direct tunneling regime, they are less important in the Fowler-Nordheim regime

Silicon Nanocrystal Field-Effect Light-Emitting Devices

We describe the operation of a light-emitting device in which silicon nanocrystals are electrically pumped via the field-effect electroluminescence (EL) mechanism. In contrast to the simultaneous bipolar carrier injection used in conventional p-n junction light-emitting diodes, this device employs sequential unipolar programming of both electrons and holes across a tunneling barrier from the same semiconductor channel. Light emission is strongly correlated with the injection of second carriers into nanocrystals that have been previously programmed with charges of the opposite sign. The properties of this device are well described by the model of a charge injection through Coulomb field modified tunneling processes. We additionally consider limiting performance bounds for potential future devices fabricated from nanocrystals with different radiative emission rates

Application and evaluation of the RF charge-pumping technique

In this paper, we will discuss the extendibility of the charge-pumping (CP) technique toward frequencies up to 4 GHz. Such high frequencies are attractive when a significant gate leakage current flows, obscuring the CP current at lower pumping frequencies.\ud It is shown that using RF gate excitation, accurate CP curves can be obtained on MOS devices with a leakage current density exceeding 1 A•cm−2 . A theoretical analysis of the trap response to RF gate voltage signals is presented, giving a clear insight on the benefits and limitations of the technique.\u

Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study

In this paper, we present a detailed simulation study of the influence of quantum mechanical effects in the inversion layer on random dopant induced threshold voltage fluctuations and lowering in sub-100 mn MOSFETs. The simulations have been performed using a three-dimensional (3-D) implementation of the density gradient (DG) formalism incorporated in our established 3-D atomistic simulation approach. This results in a self-consistent 3-D quantum mechanical picture, which implies not only the vertical inversion layer quantization but also the lateral confinement effects related to current filamentation in the “valleys” of the random potential fluctuations. We have shown that the net result of including quantum mechanical effects, while considering statistical dopant fluctuations, is an increase in both threshold voltage fluctuations and lowering. At the same time, the random dopant induced threshold voltage lowering partially compensates for the quantum mechanical threshold voltage shift in aggressively scaled MOSFETs with ultrathin gate oxides