Design of Two Phase Sinusoidal Power Clock using Adiabatic Switching

"Adiabatic" is a term of Greek origin that has spent most of its history associated with classical thermodynamics. It refers to a system in which a transition occurs without energy usually in the form of heat being either lost to or gained from the system. In the context of electronic systems, rather than heat, electronic charge is preserved. Thus, an ideal adiabatic circuit would operate without the loss or gain of electronic charge. Hence, in this work the two phase sinusoidal power clock is designed using Adiabatic switching

Implementation of Power Clock Generation Method for Pass-Transistor Adiabatic Logic 4:1 MUX

we proposed a sinusoidal single phase power clock generation method for 4:1 MUX which is designed in adiabatic logic form. For the power clock generation we presented radio frequency (3 KHz to 3 GHz) DC-AC converter. We have also obtained square wave from RC square wave oscillator consisting of cascaded NOT gates. This square wave and its inverted and phase shifted version are used as gate-drive signals for MOSFET switches those are used in the LC sine wave resonant circuit. The obtained power clock is then applied to a 4:1 MUX which is implemented in Pass-transistor Adiabatic Logic (PAL) style to illustrate power saving. It is observed that PAL 4:1 MUX is about 2 times more power efficient than that of conventional CMOS 4:1 MUX. If for 4:1 MUX, PAL logic is implemented in place of conventional CMOS logic, power saving per MUX that is achieved is about 47%. A 1 µm technology with ml2_20 as library is used for obtaining simulation results. DOI: 10.17762/ijritcc2321-8169.15060

Exact solution to the steady-state dynamics of a periodically-modulated resonator

We provide an analytic solution to the coupled-mode equations describing the steady-state of a single periodically-modulated optical resonator driven by a monochromatic input. The phenomenology of this system was qualitatively understood only in the adiabatic limit, i.e. for low modulation speed. However, both in and out of this regime, we find highly non-trivial effects for specific parameters of the modulation. For example, we show complete suppression of the transmission even with zero detuning between the input and the static resonator frequency. We also demonstrate the possibility for complete, lossless frequency conversion of the input into the side-band frequencies, as well as for optimizing the transmitted signal towards a given target temporal waveform. The analytic results are validated by first-principle simulations

Scalable Energy-Recovery Architectures.

Energy efficiency is a critical challenge for today's integrated circuits, especially for high-end digital signal processing and communications that require both high throughput and low energy dissipation for extended battery life. Charge-recovery logic recovers and reuses charge using inductive elements and has the potential to achieve order-of-magnitude improvement in energy efficiency while maintaining high performance. However, the lack of large-scale high-speed silicon demonstrations and inductor area overheads are two major concerns. This dissertation focuses on scalable charge-recovery designs. We present a semi-automated design flow to enable the design of large-scale charge-recovery chips. We also present a new architecture that uses in-package inductors, eliminating the area overheads caused by the use of integrated inductors in high-performance charge-recovery chips. To demonstrate our semi-automated flow, which uses custom-designed standard-cell-like dynamic cells, we have designed a 576-bit charge-recovery low-density parity-check (LDPC) decoder chip. Functioning correctly at clock speeds above 1 GHz, this prototype is the first-ever demonstration of a GHz-speed charge-recovery chip of significant complexity. In terms of energy consumption, this chip improves over recent state-of-the-art LDPCs by at least 1.3 times with comparable or better area efficiency. To demonstrate our architecture for eliminating inductor overheads, we have designed a charge-recovery LDPC decoder chip with in-package inductors. This test-chip has been fabricated in a 65nm CMOS flip-chip process. A custom 6-layer FC-BGA package substrate has been designed with 16 inductors embedded in the fifth layer of the package substrate, yielding higher Q and significantly improving area efficiency and energy efficiency compared to their on-chip counterparts. From measurements, this chip achieves at least 2.3 times lower energy consumption with better area efficiency over state-of-the-art published designs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116653/1/terryou_1.pd

Energy efficiency of 2- Step power-clocks for adiabatic logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parameters such as tank-capacitance to load capacitance ratio, ramping time, transistors sizing and power supply voltage scaling on energy recovery achievable in the 2-step charging circuit. We show that energy recovery achievable in the 2-step charging circuit depends on the tank-capacitor and load capacitor size concluding that tank-capacitance (CT) versus load capacitance (CL) is the significant parameter. We also show that the energy performance depends on the ramping time and improves for higher ramping times (lower frequencies). Energy recovery also improves if the transistors sizes in the step charging circuit are sized at their minimum dimensions. Lastly, we show that energy recovery decreases as the power supply voltage is scaled down. Specifically, the decrease in the energy recovery with decreasing power supply is significant for lower ramping times (higher frequencies). We propose that a Ct/Cl ratio of 10, keeping the width of the transistors in the step charging circuit minimum, can be chosen as a convenient `rule-of-thumb' in practical designs

Research on low power technology by AC power supply circuits

制度:新 ; 報告番号:甲3692号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6060Waseda Universit

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR