Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Circuit techniques for low-voltage and high-speed A/D converters

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.reviewe

Low voltage techniques for pipelined analog-to-digital converters

To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a fully-differential implementation of the OpAmp Reset Switching Technique (ORST) as a suitable low voltage design solution. The technique uses a true fully differential MDAC structure with a switching common-mode feedback to achieve increased linearity and noise performance over the previously published ORST. A pipelined ADC test chip is designed to implement the fully differential ORST technique as a proof of concept. The design also includes a simple, low power input sampling network that also allows an increased input signal range and saves power by removing the dedicated, front-end S/H. Prototype performance demonstrates the fully differential ORST and shows sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for an 8-bit ENOB in a 0.18 μm CMOS process with a 1 V supply. Little change in distortion is observed up to 90 MHz input frequency, demonstrating operation without a S/H

Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps

This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired signal on a capacitor during an "estimate" phase, and subtracting the signal from the active circuitry (typically an opamp) during a "level shift" phase. This is done within the confines of a feedback loop. The effective loop-gain is the product of the loop-gains during the estimate and level shift phases. This enables, for example, a two-stage opamp to have the accuracy of a four-stage opamp. It also enables full utilization of the power supply since the gain block's output voltage can exceed the power supply. The thesis shows that the full utilization of the power supply and the increased DC effective loop gain leads to a significant power savings compared to existing techniques. The methods are presented in the context of pipelined analog-to-digital converters, although the methods can be used with other circuits that use opamps or are sensitive to component mismatch. An overview of the detrimental effects of reduced signal swing and low DC gain is given with an emphasis on the cost in power to correct these deficiencies when limited to existing circuit techniques. CLS is then shown to correct these deficiencies without increasing power. A detailed explanation of CLS operation is given, as are measured results from a 12-bit pipelined analog-to-digital converter that was fabricated using a 0.18μ CMOS process. The results include greater than 10-bit performance with true rail-to-rail operation. An overview of calibration is also given and the limitations are discussed. An argument is made that using CLS in addition to calibration will reduce power by increasing signal-to-noise ratio and reducing and linearizing the errors due to finite opamp gain. In addition, a method to reduce the effects of mismatch by measuring the relative size of elements is presented. Finally, several avenues for future research into CLS are given

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.This work has been partially funded by Spanish Ministerio de Ciencia e Innovación (MCI), Agencia Estatal de Investigación (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-B-C3

Amplifier performance enhancement methods using positive feedback techniques

The dramatic growth in the hi-tech sector of consumer market has created many unprecedented challenges in the area of integrated circuits. The present and future communication and entertainment systems including high speed cable and DSL modems, broadband wired and wireless systems, and high definition visual products require very fast and high accuracy amplifiers, data converters and filters. Analog design in the new digital CMOS submicron processes is becoming an economical necessity in the industry. The task of building fast Op-Amp with very high DC-gain is already a very difficult problem, and this task has become more difficult using these new submicron digital processes, where traditional gain enhancement techniques are loosing their ability to deliver amplifiers with sufficient gain. In this work three new methods of implementing the internal positive-feedback to build very high DC-gain amplifiers with very low gain sensitivity to signal swings are presented. Amplifiers proposed in the first method have very high current-controlled gain. A DC gain larger than 100dB is possible without limiting the speed of the amplifier. Amplifiers proposed in the second method exhibit both enhanced speed, i.e., unity gain frequency, and enhanced gain. Amplifiers proposed in the third method have self-adjusting gain without extra control block. An implementation of a 3 bit multiplying DAC in a 9-bit 165MS/s pipeline ADC built in a 1.8V, 0.21mu digital CMOS process using one of the proposed amplifiers is described. Test results show high gain with very fast settling