Modeling and Applications of Hydrogenated Amorphous Silicon Thin Film Transistors

Very recently, the hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) has shown its important application as an on-board driver for large-area flat-panel liquid crystal displays. It is also highly desirable to have on-board TFT logic circuits adjacent to the TFT driver matrix and have them implemented in the same technology on the same substrate. This reduces the number of lead connections to the display and hence the cost, and increases the reliability of the display. The first area to be investigated is the modeling of ID vs. VD static output characteristics of the n-channel a-Si:H TFT. Second, ambipolar characteristics of the a-Si:H TFT are investigated and modeled. Thereby device models for CAD circuit simulation programs are made available for circuit design. Third, a novel CMOS-like inverter circuit is presented as an application of the ambipolar a-Si:H TFT, and its static characteristics are analytically modeled. The transient response of the TFT is also characterized and modeled in order to understand its device limitations and to quantify its speed. Finally, the dynamic characteristics of the ambipolar a-Si:H TFT inverter are investigated and modeled so that its switching speed can be predicted and the optimized inverter can be designed

Two-Dimensional Simulation of Switch-On Speeds in Hydrogenated Amorphous Silicon Thin-Film Transistors

We report accurate two-dimensional simulations of switch-on speeds in hydrogenated amorphous silicon thin-film transistors. The trap charge density along, or transverse to, the direction of semiconductor channel is highly nonuniform and the trap filling time dominates the switching time as compared to the transit time, which is about four orders of magnitude smaller. Near both contacts, direction of the transverse current is always upwards toward the insulator-semiconductor interface due to the strong electric fields. However, at the central region of the channel, the transient current is quite complex and is discussed here. When the channel length varies from 2 to 10 µm, the switching-on time is of the order of 10-3 s. The occupation function everywhere displays a partial filling of higher-energy trap states during the switch-on. This is in contrast to results presented by other investigators. Finally, the relationship between the transit time and the switch-on time with respect to the amount of trap states is discussed

Study of a-Si crystallization dependence on power and irradiation time using a CW green laser

An advantage of laser crystallization over conventional heating methods is its ability to limit rapid heating and cooling to thin surface layers. Laser energy is used to heat the a-Si thin film to change the microstructure to poly-Si. Thin film samples of a-Si were irradiated with a CW-green laser source. Laser irradiated spots were produced by using different laser powers and irradiation times. These parameters are identified as key variables in the crystallization process. The power threshold for crystallization is reduced as the irradiation time is increased. When this threshold is reached the crystalline fraction increases lineally with power for each irradiation time. The experimental results are analysed with the aid of a numerical thermal model and the presence of two crystallization mechanisms are observed: one due to melting and the other due to solid phase transformation

Development and modeling of a low temperature thin-film CMOS on glass

The push to develop integrated systems using thin-film transistors (TFT) on insulating substrates (i.e. glass) has always been limited due to low-mobility semiconducting films such as amorphous and polycrystalline silicon. Corning Incorporated is developing a new substrate material known as silicon-on-glass (SiOG). It is intrinsically better than amorphous and polycrystalline silicon materials due to its single crystal nature of the silicon film. This however does not mitigate the challenges associated with low temperature CMOS process and fabrication. The first generation of TFTs fabricated at RIT showed the potential of SiOG as a viable substrate material, but were plagued by considerable short comings such as high leakage and low transconductance. As part of this study, refinements to TFT processing on SiOG have demonstrated significant improvement to TFT performance and uniformity, showing increase transconductanace/mobility, lower subthreshold swing, tighter VT distributions, and near symmetrical NFET and PFET operation about 0 V. With these improvements minimal steps have been added to the manufacturing process, keeping simple and adoptable by the flat panel display (FPD) industry. Device modeling clearly demonstrates the key areas important to electrical operation, such as dopant activation, interface charge/trap reduction, and workfunction engineering. It addition, modeling and simulation have helped to explain the governing physics of device operation explaining non-ideal effects such as gate induced drain leakage (GIDL) and various mobility degradation mechanism. An overview of device design, process refinements and device operation is presented. Process modifications and resulting benefits are discussed along with CMOS integration on SiOG

Two-Dimensional Current Transient and Trap-State Filling of Amorphous Silicon Thin-Film Transistors

Two-dimensional simulations of amorphous silicon thin-film transistors are presented for the case when source-drain voltage is turned on long before gate voltage is turned on. Discrepancies between these results and the one-dimensional results of M. F. Willums, M. Hack, P. G. LeComber, and J. G. Shaw [MRS Symp. Proc. 258, 985 (1992)] are discussed. Valid reasons for drain current decay are provided, and occupation dynamics for the trap states are shown in order to distinguish these from the one-dimensional results of C. van Berkel, J. R. Hughes, and M. J. Powell [J. Appl. Phys. 66, 4488 (1989)] where a two-fluid model occupation function was assumed. The invalidity of such approximation is explicitly demonstrated. The mean trap-filling energy level moves up in three stages: First, the level varies with log t, then varies linearly with t, and finally, with log (log t) to a steady-state level

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Investigation on solid-phase crystallization techniques for low temperature polysilicon thin-film transistors

Low-temperature polysilicon (LTPS) has emerged as a dominant technology for high performance thin-film transistors (TFTs) used in mobile liquid crystal display (LCD) and organic light emitting diode (OLED) display products. As users demand higher quality in flat panel displays with a larger viewing area and finer resolution, the improvement in carrier mobility of LTPS compared to that of hydrogenated amorphous silicon (a-Si:H) makes it an excellent candidate as a channel material for TFT. Advantages include improvements in switching speed and the ability to incorporate peripheral scan and data driver circuitry onto a low cost display substrate. Solid-phase crystallization (SPC) is a useful technique to realize polysilicon films due to its simplicity and low cost compared to excimer-laser annealing (ELA),which has many challenges in back-plane manufacturing on large glass panels.Metal induced crystallization (MIC) results in polycrystalline silicon films with grain size as large as tens of microns. Flash-lamp annealing (FLA) is a new and novel method to crystallize a-Si films at high temperature without distortion of the glass substrate by performing an annealing within millisecond range.This work investigates SPC, MIC and FLA techniques to realize LTPS films. In addition, TFTs were designed and fabricated to characterize the device quality of the semiconductor layer, and to compare the performance of different structural arrangements

Amorphous In-Ga-Zn-O Thin-Film Transistors for Next Generation Ultra-High Definition Active-Matrix Liquid Crystal Displays.

Next generation ultra-high definition (UHD) active-matrix flat-panel displays have resolutions of 3840x2160 (4K) or 7680x4320 (8K) pixels shown at 120 Hz. The UHD display is expected to bring about immersive viewing experiences and perceived realness. The amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) is a prime candidate to be the backplane technology for UHD active-matrix liquid crystal displays (AM-LCDs) because it simultaneously fulfills two critical requirements: (i) sufficiently high field-effect mobility and (ii) uniform deposition in the amorphous phase over a large area. We have developed a robust a-IGZO density of states (DOS) model based on a combination of experimental results and information available in the literature. The impact of oxygen partial pressure during a-IGZO deposition on TFT electrical properties/instability is studied. Photoluminescence (PL) spectra are measured for a IGZO thin films of different processing conditions to identify the most likely electron-hole recombination. For the first time, we report the PL spectra measured within the a IGZO TFT channel region, and differences before/after bias-temperature stress (BTS) are compared. To evaluate the reliability of a-IGZO TFTs for UHD AM-LCD backplane, we have studied its ac BTS instability using a comprehensive set of conditions including unipolar/bipolar pulses, frequency, duty cycle, and drain biases. The TFT dynamic response, including charging characteristics and feedthrough voltage, are studied within the context of 4K and 8K UHD AM-LCD and are compared with hydrogenated amorphous silicon technology. We show that the a-IGZO TFT is fully capable of supporting 8K UHD at 480 Hz. In addition, it is feasible to reduce a-IGZO TFT feedthrough voltage by controlling for non-abrupt TFT switch-off.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111526/1/ekyu_1.pd