A universal computer control system for motors

A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor

Robust low-power digital circuit design in nano-CMOS technologies

Device scaling has resulted in large scale integrated, high performance, low-power, and low cost systems. However the move towards sub-100 nm technology nodes has increased variability in device characteristics due to large process variations. Variability has severe implications on digital circuit design by causing timing uncertainties in combinational circuits, degrading yield and reliability of memory elements, and increasing power density due to slow scaling of supply voltage. Conventional design methods add large pessimistic safety margins to mitigate increased variability, however, they incur large power and performance loss as the combination of worst cases occurs very rarely. In-situ monitoring of timing failures provides an opportunity to dynamically tune safety margins in proportion to on-chip variability that can significantly minimize power and performance losses. We demonstrated by simulations two delay sensor designs to detect timing failures in advance that can be coupled with different compensation techniques such as voltage scaling, body biasing, or frequency scaling to avoid actual timing failures. Our simulation results using 45 nm and 32 nm technology BSIM4 models indicate significant reduction in total power consumption under temperature and statistical variations. Future work involves using dual sensing to avoid useless voltage scaling that incurs a speed loss. SRAM cache is the first victim of increased process variations that requires handcrafted design to meet area, power, and performance requirements. We have proposed novel 6 transistors (6T), 7 transistors (7T), and 8 transistors (8T)-SRAM cells that enable variability tolerant and low-power SRAM cache designs. Increased sense-amplifier offset voltage due to device mismatch arising from high variability increases delay and power consumption of SRAM design. We have proposed two novel design techniques to reduce offset voltage dependent delays providing a high speed low-power SRAM design. Increasing leakage currents in nano-CMOS technologies pose a major challenge to a low-power reliable design. We have investigated novel segmented supply voltage architecture to reduce leakage power of the SRAM caches since they occupy bulk of the total chip area and power. Future work involves developing leakage reduction methods for the combination logic designs including SRAM peripherals

Phase sensitive guidance sensor for wire-following vehicles

A guidance sensor for a wire-following vehicle which is phase sensitive, includes an array of coils positioned to sense the vertical component of a magnetic field produced by the ac current through the guidance wire. The outputs of the coils are fed to associated flip flops. Flip flops associated with coils, through which flux passes in one direction, e.g., up, are driven to one state, e.g., true, and flip flops associated with coils through which flux passes in the opposite direction, e.g., down, are driven to a false state. The control signal to guide the vehicle over the wire is a function of the number of flip flops in the true state. Circuitry is included to prevent flip flops from assuming a wrong state due to noise

High Performance Low Power Dual Edge Triggered Static D Flip-Flop

In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence require lesser number of transistors and thus requires lesser overall silicon area.DOI:http://dx.doi.org/10.11591/ijece.v3i5.316

Low Power Explicit Pulse Triggered Flip-Flop Design Based On A Pass Transistor

In VLSI system design, power consumption is the ambitious issue for the past respective years. Advanced IC fabrication technology grants the use of nano scaled devices, so the power dissipation becomes major problem in the designing of VLSI chips. In this paper we present, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme using pass transistor. The offered design successfully figure out the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better power performance by consuming low power. The proposed design also significantly reduces delay time, set-up time and hold time. Simulation results based on TMC 180nm CMOS technology reveal that the proposed design features the best power and delay performance in several FF designs under comparison

Design and Robustness Analysis on Non-volatile Storage and Logic Circuit

By combining the flexibility of MOS logic and the non-volatility of spintronic devices, spin-MOS logic and storage circuitry offer a promising approach to implement highly integrated, power-efficient, and nonvolatile computing and storage systems. Besides the persistent errors due to process variations, however, the functional correctness of Spin-MOS circuitry suffers from additional non-persistent errors that are incurred by the randomness of spintronic device operations, i.e., thermal fluctuations. This work quantitatively investigates the impact of thermal fluctuations on the operations of two typical Spin-MOS circuitry: one transistor and one magnetic tunnel junction (1T1J) spin-transfer torque random access memory (STT-RAM) cell and a nonvolatile latch design. A new nonvolatile latch design is proposed based on magnetic tunneling junction (MTJ) devices. In the standby mode, the latched data can be retained in the MTJs without consuming any power. Two types of operation errors can occur, namely, persistent and non-persistent errors. These are quantitatively analyzed by including models for process variations and thermal fluctuations during the read and write operations. A mixture importance sampling methodology is applied to enable yield-driven design and extend its application beyond memories to peripheral circuits and logic blocks. Several possible design techniques to reduce thermal induced non-persistent error rate are also discussed