2 research outputs found
A high-performance inner-product processor for real and complex numbers.
A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is investigated in this dissertation. This scheme decreases the number of partial products to 50%, while achieving better speed and area performance, as well as providing pipeline extension opportunities. When modified Booth coding is used, partial products are reduced by almost 75%, thereby significantly reducing the multiplier addition depth. The design is applicable for digital signal and image processing applications that require real and/or complex numbers inner-product arithmetic, such as digital filters, correlation and convolution. This design is well suited for VLSI implementation and can also be embedded as an inner-product core inside a general purpose or DSP FPGA-based processor. Dynamic control of the computing structure permits different computations, such as a variety of inner-product real and complex number computations, parallel multiplication for real and complex numbers, and real and complex number division. The same structure can also be controlled to accept redundant binary number inputs for multiplication and inner-product computations. An improved 2's-complement to redundant binary converter is also presented
Numerical solutions of differential equations on FPGA-enhanced computers
Conventionally, to speed up scientific or engineering (S&E) computation programs
on general-purpose computers, one may elect to use faster CPUs, more memory, systems
with more efficient (though complicated) architecture, better software compilers, or even
coding with assembly languages. With the emergence of Field Programmable Gate
Array (FPGA) based Reconfigurable Computing (RC) technology, numerical scientists
and engineers now have another option using FPGA devices as core components to
address their computational problems. The hardware-programmable, low-cost, but
powerful “FPGA-enhanced computer” has now become an attractive approach for many
S&E applications.
A new computer architecture model for FPGA-enhanced computer systems and its
detailed hardware implementation are proposed for accelerating the solutions of
computationally demanding and data intensive numerical PDE problems. New FPGAoptimized
algorithms/methods for rapid executions of representative numerical methods
such as Finite Difference Methods (FDM) and Finite Element Methods (FEM) are
designed, analyzed, and implemented on it. Linear wave equations based on seismic
data processing applications are adopted as the targeting PDE problems to demonstrate
the effectiveness of this new computer model. Their sustained computational
performances are compared with pure software programs operating on commodity CPUbased
general-purpose computers. Quantitative analysis is performed from a hierarchical
set of aspects as customized/extraordinary computer arithmetic or function units, compact but flexible system architecture and memory hierarchy, and hardwareoptimized
numerical algorithms or methods that may be inappropriate for conventional
general-purpose computers. The preferable property of in-system hardware
reconfigurability of the new system is emphasized aiming at effectively accelerating the
execution of complex multi-stage numerical applications. Methodologies for
accelerating the targeting PDE problems as well as other numerical PDE problems, such
as heat equations and Laplace equations utilizing programmable hardware resources are
concluded, which imply the broad usage of the proposed FPGA-enhanced computers