A Low-Voltage Electronically Tunable MOSFET-C Voltage-Mode First-Order All-Pass Filter Design

This paper presents a simple electronically tunable voltage-mode first-order all-pass filter realization with MOSFET-C technique. In comparison to the classical MOSFET-C filter circuits that employ active elements including large number of transistors the proposed circuit is only composed of a single two n-channel MOSFET-based inverting voltage buffer, three passive components, and one NMOS-based voltage-controlled resistor, which is with advantage used to electronically control the pole frequency of the filter in range 103 kHz to 18.3 MHz. The proposed filter is also very suitable for low-voltage operation, since between its supply rails it uses only two MOSFETs. In the paper the effect of load is investigated. In addition, in order to suppress the effect of non-zero output resistance of the inverting voltage buffer, two compensation techniques are also introduced. The theoretical results are verified by SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters, where +/- 0.45 V supply voltages are used. Moreover, the behavior of the proposed filter was also experimentally measured using readily available array transistors CD4007UB by Texas Instruments

Design of a Magnetically Tunable Low Noise Amplifier in 0.13 um CMOS Technology

With legacy technologies present and approaching new wireless standards, the 1-10 GHz band of frequencies is quickly becoming saturated. Although saturated, the frequency bands are being utilized inefficiently. Cognitive radio, an intelligent wireless communication system, is the novel solution for the efficient utilization of the frequency bands. Front-end receivers for cognitive radio will need the capability to receive and process multiple frequency bands and a key component is the low noise amplifier (LNA). A tunable LNA using a new magnetically tuned input impedance matching network is presented. The LNA has been designed and simulated in a commercially available 0.13 μm CMOS technology and is capable of tuning from 3.2 GHz to 4.6 GHz as S11 \u3c -10 dB. Within this bandwidth the maximum power gain is 16.2 dB, the maximum noise figure is 7.5 dB, and the minimum IIP3 is -6.4 dBm. The total power consumption of the LNA (neglecting the buffer required to drive the 50 Ω test equipment) is 50 mW. This tunable LNA introduces a new magnetically tunable matching technique and tuning scheme capable of continuous frequency variation for LNAs. It is expected that this technique could be expanded to realize LNAs with a tunable, narrow-band response that can cover the entire 1-10 GHz band of frequencies. The presented tunable LNA has demonstrated the capability to cover and process multiple frequencies and can be used for reconfigurable systems. A tunable LNA design is the first step in an effort to realize a fully reconfigurable front-end radio frequency (RF) receiver for future cognitive radio applications

Novel ring resonator-based optical beamformer system and experimental results

A novel squint-free, continuously tunable beamformer mechanism for a phased array antenna system is proposed. It consists of filter-based optical single-sideband suppressed-carrier modulation, a fully integrated optical beam forming network using cascades of optical ring resonators as tunable delay elements, and balanced coherent optical detection. The proposed system brings advantages in optical bandwidth requirement, system complexity, and dynamic range, without introducing the problem of beam squint or limited tuning resolution. Some experimental results are presented in order to demonstrate the feasibility of the proposed concept

10 GHz Low Loss Liquid Metal SIW Phase Shifter for Phased Array Antenna

This paper presents a proof of concept demonstrator for a pair of novel phase shifters based on substrate integrated waveguide (SIW) technology. Gallium-based liquid metal (LM) is used to reconfigure each phase shifter. The paper presents LM phase shifters that, for the first time, have a phase shifting range of 360⁰. The phase shifters have a small electrical size, and they are intended for use within phased array antenna applications. The paper also presents a design procedure for the phase shifters. The procedure has been used to design two phase shifters operating at 10 GHz. The design process can be readily scaled for operation at other frequencies. The proposed phase shifters are reciprocal and bidirectional and they have very low insertion loss. A series of reconfigurable LM vias are used to achieve the phase shift. Each of LM via is activated once a drill hole is filled with LM and it is deactivated once LM is removed. Using this method; it is possible to achieve a phase shift step ranging from 1° to 100° using a single LM via. Moreover, the overall phase shift can be extended to 360° by employing several LM vias in series inside the SIW. The proposed phase shifters have an insertion loss lower than 3 dB and provide a total phase shifting range of approximately 360° in eight steps of approximately 45° each. This enables the proposed two phase shifters to have an extraordinary Figure of Merit (FoM) of 131.3 ⁰/dB and 122.4 ⁰/dB

Transmetteurs photoniques sur silicium pour les transmissions optiques à grande capacité

Les applications exigeant des très nombreuses données (médias sociaux, diffusion vidéo en continu, mégadonnées, etc.) se développent à un rythme rapide, ce qui nécessite de plus en plus de liaisons optiques ultra-rapides. Ceci implique le développment des transmetteurs optiques intégrés et à bas coût et plus particulirement en photonique sur silicium en raison de ses avantages par rapport aux autres technologies (LiNbO3 et InP), tel que la compatibilité avec le procédé de fabrication CMOS. Les modulateurs optoélectronique sont un élément essentiel dans la communication op-tique. Beaucoup de travaux de recherche sont consacrées au développement de dispositifs optiques haut débit efficaces. Cependant, la conception de modulateurs en photonique sur sili-cium (SiP) haut débit est diffcile, principalement en raison de l'absence d'effet électro-optique intrinsèque dans le silicium. De nouvelles approches et de architectures plus performances doivent être développées afin de satisfaire aux critères réliés au système d'une liaison optique aux paramètres de conception au niveau du dispositif integré. En outre, la co-conception de circuits integrés photoniques sur silicium et CMOS est cruciale pour atteindre tout le potentiel de la technologie de photonique sur silicium. Ainsi cette thèse aborde les défits susmentionnés. Dans notre première contribution, nous préesentons pour la première fois un émetteur phononique sur silicium PAM-4 sans utiliser un convertisseur numérique analog (DAC)qui comprend un modulateur Mach Zehnder à électrodes segmentées SiP (LES-MZM) implémenté dans un procédé photonique sur silicium générique avec jonction PN latérale et son conducteur CMOS intégré. Des débits allant jusqu'à 38 Gb/s/chnnel sont obtenus sans utili-ser un convertisseur numérique-analogique externe. Nous présentons également une nouvelle procédure de génération de délai dans le excitateur de MOS complémentaire. Un effet, un délai robuste aussi petit que 7 ps est généré entre les canaux de conduite. Dans notre deuxième contribution, nous présentons pour la première fois un nouveau fac-teur de mérite (FDM) pour les modulateurs SiP qui inclut non seulement la perte optique et l'efficacité (comme les FDMs précédents), mais aussi la bande passante électro-optique du modulateur SiP (BWEO). Ce nouveau FDM peut faire correspondre les paramètres de conception physique du modulateur SiP à ses critères de performance au niveau du système, facilitant à la fois la conception du dispositif optique et l'optimisation du système. Pour la première fois nous définissons et utilisons la pénalité de puissance du modulateur (MPP) induite par le modulateur SiP pour étudier la dégradation des performances au niveau du système induite par le modulateur SiP dans une communication à base de modulation d'amplitude d'impulsion optique. Nous avons développé l'équation pour MPP qui inclut les facteurs de limitation du modulateur (perte optique, taux d'extinction limité et limitation de la bande passante électro-optique). Enfin, dans notre troisième contribution, une nouvelle méthodologie de conception pour les modulateurs en SiP intégré à haute débit est présentée. La nouvelle approche est basée sur la minimisation de la MPP SiP en optimisant l'architecture du modulateur et le point de fonctionnement. Pour ce processus, une conception en longueur unitaire du modulateur Mach Zehnder (MZM) peut être optimisée en suivant les spécifications du procédé de fabrication et les règles de conception. Cependant, la longueur et la tension de biais du d'éphaseur doivent être optimisées ensemble (par exemple selon vitesse de transmission et format de modulation). Pour vérifier l'approche d'optimisation proposée expérimentale mont, a conçu un modulateur photonique sur silicium en phase / quadrature de phase (IQ) ciblant le format de modulation 16-QAM à 60 Gigabaud. Les résultats expérimentaux prouvent la fiabilité de la méthodologie proposée. D'ailleurs, nous avons augmenté la vitesse de transmission jusqu'à 70 Gigabaud pour tester la limite de débit au système. Une transmission de données dos à dos avec des débits binaires de plus de 233 Gigabit/s/channel est observée. Cette méthodologie de conception ouvre ainsi la voie à la conception de la prochaine génération d'émetteurs intégrés à double polarisation 400+ Gigabit/s/channel.Data-hungry applications (social media, video streaming, big data, etc.) are expanding at a fast pace, growing demand for ultra-fast optical links. This driving force reveals need for low-cost, integrated optical transmitters and pushes research in silicon photonics because of its advantages over other platforms (i.e. LiNbO3 and InP), such as compatibility with CMOS fabrication processes, the ability of on-chip polarization manipulation, and cost effciency. Electro-optic modulators are an essential component of optical communication links and immense research is dedicated to developing effcient high-bitrate devices. However, the design of high-capacity Silicon Photonics (SiP) transmitters is challenging, mainly due to lack of inherent electro-optic effect in silicon. New design methodologies and performance merits have to be developed in order to map the system-level criteria of an optical link to the design parameters in device-level. In addition, co-design of silicon photonics and CMOS integrated circuits is crucial to reveal the full potential of silicon photonics. This thesis addresses the aforementioned challenges. In our frst contribution, for the frst time we present a DAC-less PAM-4 silicon photonic transmitter that includes a SiP lumped-element segmented-electrode Mach Zehnder modula-tor (LES-MZM) implemented in a generic silicon photonic process with lateral p-n junction and its co-designed CMOS driver. Using post processing, bitrates up to 38 Gb/s/channel are achieved without using an external digital to analog converter. We also presents a novel delay generation procedure in the CMOS driver. A robust delay as small as 7 ps is generated between the driving channels. In our second contribution, for the frst time we present a new figure of merit (FOM) for SiP modulators that includes not only the optical loss and effciency (like the prior FOMs), but also the SiP modulator electro-optic bandwidth ( BWEO). This new FOM can map SiP modulator physical design parameters to its system-level performance criteria, facilitating both device design and system optimization. For the frst time we define and employ the modulator power penalty (MPP) induced by the SiP modulator to study the system level performance degradation induced by SiP modulator in an optical pulse amplitude modulation link. We develope a closed-form equation for MPP that includes the SiP modulator limiting factors (optical loss, limited extinction ratio and electro-optic bandwidth limitation). Finally in our third contribution, we present a novel design methodology for integrated high capacity SiP modulators. The new approach is based on minimizing the power penalty of a SiP modulator (MPP) by optimizing modulator design and bias point. For the given process, a unit-length design of Mach Zehnder modulator (MZM) can be optimized following the process specifications and design rules. However, the length and the bias voltage of the phase shifter must be optimized together in a system context (e.g., baud rate and modulation format). Moreover, to verify the proposed optimization approach in experiment, we design an in-phase/quadrature-phase (IQ) silicon photonic modulator targeting 16-QAM modulation format at 60 Gbaud. Experimental results proves the reliability of our proposed methodology. We further push the baud rate up to 70 Gbaud to examine the capacity boundary of the device. Back to back data transmission with bitrates more than 233 Gb/s/channel are captured. This design methodology paves the way for designing the next generation of integrated dual- polarization 400+ Gb/s/channel transmitters

Phased array receive antenna steering system using a ring resonator-based optical beam forming network and filter-based optical SSB-SC modulation

A novel phased array receive antenna steering system is introduced. The core of this system is an optical ring resonator-based broadband, continuously tunable optical beam forming network (OBFN). In the proposed system architecture, filter-based optical single-sideband suppressed-carrier modulation and balanced coherent optical detection are used. \ud Such architecture has significant advantages over a straightforward architecture using optical double-sideband modulation and direct optical detection, namely relaxed bandwidth requirements on the optical modulators and detectors, reduced complexity of the OBFN chip, and enhanced dynamic range. Initial measurements on an actual 1×8 OBFN chip and an optical sideband filter chip are presented. Both are realized in CMOS-compatible planar optical waveguide technology.\u

Realization of Low-Voltage Modified CBTA and Design of Cascadable Current-Mode All-Pass Filter

In this paper, a low voltage modified current backward transconductance amplifier (MCBTA) and a novel first-order current-mode (CM) all-pass filter are presented. The MCBTA can operate with ±0.9 V supply voltage and the total power consumption of MCBTA is 1.27 mW. The presented all-pass filter employs single MCBTA, a grounded resistor and a grounded capacitor. The circuit possesses low input and high output impedances which make it ideal for current-mode systems. The presented all-pass filter circuit can be made electronically tunable due to the bias current of the MCBTA. Non-ideal study along with simulation results are given for validation purpose. Further, an nth-order cascadable all-pass filter is also presented. It uses n MCBTAs, n grounded resistors and n grounded capacitors. The performance of the proposed circuits is demonstrated by using PSPICE simulations based on the 0.18 µm TSMC level-7 CMOS technology parameters