Design of multiplierless correlators for timing synchronization in IEEE 802.11a wireless LANs

Timing synchronization for IEEE 802.11a WLANs requires using a correlator to correlate the received signal with a known waveform. Straightforward implementation of this correlator results in the need to perform 320 million complex multiplications per second. This significant requirement can be eliminated by using multiplierless correlators. In this paper, multiplierless correlators are designed based on constraining the real and imaginary parts of correlator coefficients to be sums of powers of two. Sets of coefficients that yield good synchronization performance for simple A WGN channels are first identified; then their goodness for indoor communication environments is verified by simulation for multipath fading channels. Several multiplierless correlators are found. Comparison among these correlators identifies a good one that requires to perform only 26 addition/subtraction operations per correlator output while a similar synchronization performance can be maintained.published_or_final_versio

Multi-carrier transmission techniques toward flexible and efficient wireless communication systems

制度:新 ; 文部省報告番号:甲2562号 ; 学位の種類:博士(国際情報通信学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新470

Near-Instantaneously Adaptive HSDPA-Style OFDM Versus MC-CDMA Transceivers for WIFI, WIMAX, and Next-Generation Cellular Systems

Burts-by-burst (BbB) adaptive high-speed downlink packet access (HSDPA) style multicarrier systems are reviewed, identifying their most critical design aspects. These systems exhibit numerous attractive features, rendering them eminently eligible for employment in next-generation wireless systems. It is argued that BbB-adaptive or symbol-by-symbol adaptive orthogonal frequency division multiplex (OFDM) modems counteract the near instantaneous channel quality variations and hence attain an increased throughput or robustness in comparison to their fixed-mode counterparts. Although they act quite differently, various diversity techniques, such as Rake receivers and space-time block coding (STBC) are also capable of mitigating the channel quality variations in their effort to reduce the bit error ratio (BER), provided that the individual antenna elements experience independent fading. By contrast, in the presence of correlated fading imposed by shadowing or time-variant multiuser interference, the benefits of space-time coding erode and it is unrealistic to expect that a fixed-mode space-time coded system remains capable of maintaining a near-constant BER

Algorithm-Architecture Co-Design for Digital Front-Ends in Mobile Receivers

The methodology behind this work has been to use the concept of algorithm-hardware co-design to achieve efficient solutions related to the digital front-end in mobile receivers. It has been shown that, by looking at algorithms and hardware architectures together, more efficient solutions can be found; i.e., efficient with respect to some design measure. In this thesis the main focus have been placed on two such parameters; first reduced complexity algorithms to lower energy consumptions at limited performance degradation, secondly to handle the increasing number of wireless standards that preferably should run on the same hardware platform. To be able to perform this task it is crucial to understand both sides of the table, i.e., both algorithms and concepts for wireless communication as well as the implications arising on the hardware architecture. It is easier to handle the high complexity by separating those disciplines in a way of layered abstraction. However, this representation is imperfect, since many interconnected "details" belonging to different layers are lost in the attempt of handling the complexity. This results in poor implementations and the design of mobile terminals is no exception. Wireless communication standards are often designed based on mathematical algorithms with theoretical boundaries, with few considerations to actual implementation constraints such as, energy consumption, silicon area, etc. This thesis does not try to remove the layer abstraction model, given its undeniable advantages, but rather uses those cross-layer "details" that went missing during the abstraction. This is done in three manners: In the first part, the cross-layer optimization is carried out from the algorithm perspective. Important circuit design parameters, such as quantization are taken into consideration when designing the algorithm for OFDM symbol timing, CFO, and SNR estimation with a single bit, namely, the Sign-Bit. Proof-of-concept circuits were fabricated and showed high potential for low-end receivers. In the second part, the cross-layer optimization is accomplished from the opposite side, i.e., the hardware-architectural side. A SDR architecture is known for its flexibility and scalability over many applications. In this work a filtering application is mapped into software instructions in the SDR architecture in order to make filtering-specific modules redundant, and thus, save silicon area. In the third and last part, the optimization is done from an intermediate point within the algorithm-architecture spectrum. Here, a heterogeneous architecture with a combination of highly efficient and highly flexible modules is used to accomplish initial synchronization in at least two concurrent OFDM standards. A demonstrator was build capable of performing synchronization in any two standards, including LTE, WiFi, and DVB-H

Energy Efficiency in Communications and Networks

The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

WIMAX TESTBED

WiMAX, the Worldwide Interoperability for Microwave Access, is a telecommunications technology aimed at providing wireless data over long distances in a variety of ways, from point-to-point links to full mobile cellular type access. It is based on the IEEE 802.16 standard, which is also called Wire IessMAN. The name WiMAX was created by the WiMAX Forum, which was formed in June 2001 to promote conformance and interoperability of the standard. The forum describes WiMAX as a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. This Final Year Project attempts to simulate via Simulink, the working mechanism of a WiMAX testbed that includes a transmitter, channel and receiver. This undertaking will involve the baseband physical radio link. Rayleigh channel model together with frequency and timing offsets are introduced to the system and a blind receiver will attempt to correct these offsets and provide channel equalization. The testbed will use the Double Sliding Window for timing offset synchronization and the Schmid! & Cox algorithm for Fractional Frequency Offset estimation. The Integer Frequency Offset synchronization is achieved via correlation of the incoming preamble with its local copy whereas Residual Carrier Fr~quency Offset is estimated using the L th extension method. A linear Channel Estimator is added and combined with all the other blocks to form the testbed. From the results, this testbed matches the standard requirements for the BER when SNR is 18dB or higher. At these SNRs, the receiver side of the testbed is successful in performing the required synchronization and obtaining the same data sent. Sending data with SNR lower than 18dB compromises its performance as the channel equalizer is non-linear. This project also takes the first few steps of hardware implementation by using Real Time Workshop to convert the Simulink model into C codes which run outside MATLAB. In addition, the Double Sliding Window and Schmid! & Cox blocks are converted to Xilinx blocks and proven to be working like their Simulink counterparts

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP