Interactive Real-Time Embedded Systems Education Infused with Applied Internet Telephony

The transition from traditional circuit-switched phone systems to modern packet-based Internet telephony networks demands tools to support Voice over Internet Protocol (VoIP) development. In this paper, we introduce the XinuPhone, an integrated hardware/software approach for educating users about VoIP technology on a real-time embedded platform. We propose modular course topics for design-oriented, hands-on laboratory exercises: filter design, timing, serial communications, interrupts and resource budgeting, network transmission, and system benchmarking. Our open-source software platform encourages development and testing of new CODECs alongside existing standards, unlike similar commercial solutions. Furthermore, the supporting hardware features inexpensive, readily available components designed specifically for educational and research users on a limited budget. The XinuPhone is especially good for experimenting with design trade-offs as well as interactions between real-time software and hardware components

A low power UART design based on asynchronous techniques

pre-printAbstract-Universal Asynchronous Receiver Transmitter (UART) implements serial communication between peripherals and remote embedded systems. The UART protocol is defined based on fixed frequencies with a sampling method to achieve robustness under reasonable frequency variations between systems. Such design specifications are natural for clocked domains. This work investigates whether this simple clocked hardware protocol can be advantageously implemented using asynchronous design techniques. A full duplex clocked and asynchronous UART are implemented and compared. The asynchronous design results in average power of about one fourth that of the clocked design under standard operating modes

Design and Implementation of Reconfigurable Bus Protocol Translator/Convertor using FPGA

In systems involving multiple peripherals with diverse bus protocols it is desirable to have a versatile reconfigurable hardware platform to translate/convert a specific protocol to minimize the complexity of system design. Especially when the number of peripherals and devices are large, it is very much mandatory to have such a hardware to deal with diverse communication protocols. These requirements give rise to the need for an reconfigurable system which can act as a bridge between two devices following different communication protocols. Communication protocols such as I2C, SPI,USB and UART protocols are commonly used protocols in hardware design. In this work, such a versatile hardware solution is proposed which would translate a basic UART protocol to I2C,SPI or USB, depending upon the communication requirement. Such a system will eliminate the complexities of protocol management to the designer and it allows them to focus on application design and development. A customized hardware is designed using Altera Cyclone-II FPGA core and the protocol bridge is tested for multiple hardware engines

Formal and model driven design of the bright light therapy system Luxamet

Seasonal depression seriously diminishes the quality of life for many patients. To improve their condition, we propose LUXAMET, a bright light therapy system. This system has the potential to relieve patients from some of the symptoms caused by seasonal depression. The system was designed with a formal and model driven design methodology. This methodology enabled us to minimize systemic hazards, like blinding patients with an unhealthy dose of light. This was achieved by controlling race conditions and memory leaks, during design time. We prove that the system specification is deadlock as well as livelock free and there are no invariant violations. These proofs, together with the similarity between specification model and implementation code, make us confident that the implemented system is a reliable tool which can help patients during seasonal depression

A Review: Analysis of White Space for Designing Communication Module

In this paper we propose the literature review related to analysis of White Space for Designing Communication Module. The radio frequency spectrum is an essential factor in communication network. With demand for wireless connectivity increasing, the exploitation of white space is an attractive way of making more efficient use of radio spectrum. This paper is based on the detecting the unutilized spectrum that can safely be used for broadband communication networks

Collecting and Analyzing Failure Data of Bluetooth Personal Area Networks

This work presents a failure data analysis campaign on Bluetooth Personal Area Networks (PANs) conducted on two kind of heterogeneous testbeds (working for more than one year). The obtained results reveal how failures distribution are characterized and suggest how to improve the dependability of Bluetooth PANs. Specically, we dene the failure model and we then identify the most effective recovery actions and masking strategies that can be adopted for each failure. We then integrate the discovered recovery actions and masking strategies in our testbeds, improving the availability and the reliability of 3.64% (up to 36.6%) and 202% (referred to the Mean Time To Failure), respectively

Implementation and Characterization of AHR on a Xilinx FPGA

A new version of the Adaptive-Hybrid Redundancy (AHR) architecture was developed to be implemented and tested in hardware using Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs). The AHR architecture was developed to mitigate the effects that the Single Event Upset (SEU) and Single Event Transient (SET) radiation effects have on processors and was tested on a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. The AHR MIPS architecture was implemented in hardware using two Xilinx FPGAs. A Universal Asynchronous Receiver Transmitter (UART) based serial communication network was added to the AHR MIPS design to enable inter-board communication between the two FPGAs. The runtime performance of AHR MIPS was measured in hardware and compared against the runtime performance of standalone TMR and TSR MIPS architectures. The hardware implementation of AHR MIPS demonstrated flexible runtime performance that was nearly as fast as TMR MIPS, never as slow as TSR MIPS, and demonstrated performance in between those extremes. Hardware testing and verification of AHR MIPS showed that the AHR mitigation strategy presents a large performance tradespace, where a user can adjust both the runtime processor performance and radiation tolerance to fit the constraints of a space mission, while also continuing to provide adaptive performance based upon the current radiation environment

Educational Signal Processing Platform

Digital Signal Processing (DSP) education is often limited by the high cost to entry for the platforms commonly used in college laboratories. Since most students cannot reasonably afford a $400 board (in addition to a textbook, tuition, etc.), this project created a new DSP platform at a much more reasonable price ($50), while maintaining the same level of educational content and value. The new platform consists of hardware designed for audio processing using Microchip\u27s dsPIC33F microcontroller, as well as a set of software libraries to facilitate its use. New laboratory assignments were also formulated to achieve the same learning outcomes as the assignments that use the more expensive hardware