Two-level pipelined systolic array graphics engine

The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-¿m CMOS technolog

An architecture for interactive raster graphics

A radical reappraisal of the 3-D Interactive raster graphics pipeline has resulted In an experimental architecture for a workstation which is currently being evaluated at the CW!. The principal features of this architecture are that It: - concentrates exclusively on real-time interactive 3-D graphics (initially for CAD). - uses object space rather than Image space methods where possible. - avoids using a frame buffer. - only uses custom VLSI where commercial products are unlikely to suffice In the near term. Four years Into the project the system design Is complete and the major components have been acquired and the custom VLSI chips hove been packaged and tested. The current experience with the system is based on detailed simulations which gave a fairiy clear Idea on Its strengths and limitations. A complete, but reduced resolution, experimental prototype system is now being assembled

Design of a VLSI scan conversion processor for high performance 3-D graphics systems

Scan conversion processing is the bottleneck in the image generation process. To solve the problem of smooth shading and hidden surface elimination, a new processor architecture has been invented which has been labeled as a scan conversion processor architecture (SCP). The SCP is designed to perform hidden surface elimination and scan conversion for 64 pixels. The color intensities are dual-buffered so that when one buffer is being updated the other can be scanned out. Z-depth is used to perform the hidden surface elimination. The key operation performed by the SCP is the evaluation of linear functions of a form like F(X,Y) = A * X + B * Y + C. The computation is further simplified by using incremental addition. The z-depth buffer and the color buffers are incorporated onto the same chip. The SCP receives from its preprocessor the information for the definition of polygons and the computation of z-depth and RGB color intensities;Many copies of this processor will be used in a high performance graphics system. The SCP processes one polygon at a time. Many polygons can be processed at the same time when several Bounds-Checking Processors are added to the system. Each Bounds-Checking Processor handles a specific area of the display screen. If one polygon has intersection with a Bounds-Checking Processor\u27s controlled area, the related information will be rebroadcasted to SCPs in that area. The SCP chip uses about 26,000 transistors. 16 SCPs can be put on one chip if the 1 [mu]m CMOS technology is used

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Index to 1985 NASA Tech Briefs, volume 10, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1985 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

An instruction systolic array architecture for multiple neural network types

Modern electronic systems, especially sensor and imaging systems, are beginning to incorporate their own neural network subsystems. In order for these neural systems to learn in real-time they must be implemented using VLSI technology, with as much of the learning processes incorporated on-chip as is possible. The majority of current VLSI implementations literally implement a series of neural processing cells, which can be connected together in an arbitrary fashion. Many do not perform the entire neural learning process on-chip, instead relying on other external systems to carry out part of the computation requirements of the algorithm. The work presented here utilises two dimensional instruction systolic arrays in an attempt to define a general neural architecture which is closer to the biological basis of neural networks - it is the synapses themselves, rather than the neurons, that have dedicated processing units. A unified architecture is described which can be programmed at the microcode level in order to facilitate the processing of multiple neural network types. An essential part of neural network processing is the neuron activation function, which can range from a sequential algorithm to a discrete mathematical expression. The architecture presented can easily carry out the sequential functions, and introduces a fast method of mathematical approximation for the more complex functions. This can be evaluated on-chip, thus implementing the entire neural process within a single system. VHDL circuit descriptions for the chip have been generated, and the systolic processing algorithms and associated microcode instruction set for three different neural paradigms have been designed. A software simulator of the architecture has been written, giving results for several common applications in the field