Causapruno G.

Cofano M.

Graziano M.

Santoro G.

Turvani G.

Vacca M.

English

In the last decades transistor scaling has driven electronics toward an extraordinary evolution. The ability to squeeze millions of transistors on a single chip makes it possible to have an incredible computational power in very small size. Many computational systems are still based on the Von Neumann architecture, where computational units and memory blocks are two separate entities. Nanometer-sized transistors enable the development of incredibly fast logic units that cannot work at full speed due to limitations in data transfer from memory. To further evolve electronic circuits, new innovative architectural solutions must be developed to overcome the main limitations of current systems. In this work, we present an architectural implementation of the Logic-In-Memory (LIM) concept that we characterize by considering three data-intensive benchmarks: the odd even sort, the integral image and the binomial filter. The architecture is synthesized on a 28 nm CMOS technology and it is validated by comparing it to a previous version of the LIM structure and to conventional architectures, showing an impressive increase in performance, in terms of speed gain and power consumption reduction

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms

https://iris.polito.it/bitstream/11583/2736479/3/lim_main.pdf

Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms

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PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)