115 research outputs found

    RF CMOS quadrature voltage-controlled oscillator design using superharmonic coupling method.

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    Chung, Wai Fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (leaves 98-100).Abstracts in English and Chinese.摘要 --- p.IIIACKNOWLEDGEMENT --- p.IVCONTENTS --- p.VLIST OF FIGURES --- p.VIIILIST OF TABLES --- p.XLIST OF TABLES --- p.XChapter CHAPTER 1 --- INTRODUCTION --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Receiver Architecture --- p.3Chapter 1.2.1 --- Zero-IF Receivers --- p.4Chapter 1.2.2 --- Low-IF Receivers --- p.6Chapter 1.2.2.1 --- Hartley Architecture --- p.7Chapter 1.2.2.2 --- Weaver Architecture --- p.9Chapter 1.3 --- Image-rejection ratio --- p.10Chapter 1.4 --- Thesis Organization --- p.12Chapter CHAPTER 2 --- FUNDAMENTALS OF OSCILLATOR --- p.13Chapter 2.1 --- Basic Oscillator Theory --- p.13Chapter 2.2 --- Varactor --- p.15Chapter 2.3 --- Inductor --- p.17Chapter 2.4 --- Phase noise --- p.22Chapter 2.4.1 --- The Leeson ´ةs phase noise expression --- p.24Chapter 2.4.2 --- Linear model --- p.25Chapter 2.4.3 --- Linear Time-Variant phase noise model --- p.28Chapter CHAPTER 3 --- FULLY-INTEGRATED CMOS OSCILLATOR DESIGN --- p.31Chapter 3.1 --- Ring oscillator --- p.31Chapter 3.2 --- LC oscillator --- p.33Chapter 3.2.1 --- LC-tank resonator --- p.34Chapter 3.2.2 --- Negative transconductance --- p.36Chapter 3.3 --- Generation of quadrature phase signals --- p.39Chapter 3.4 --- Quadrature VCO topologies --- p.41Chapter 3.4.1 --- Parallel-coupled QVCO --- p.41Chapter 3.4.2 --- Series-coupled QVCO --- p.46Chapter 3.4.3 --- QVCO with Back-gate Coupling --- p.47Chapter 3.4.4 --- QVCO using superharmonic coupling --- p.49Chapter 3.5 --- Novel QVCO using back-gate superharmonic coupling --- p.52Chapter 3.5.1 --- Tuning range --- p.54Chapter 3.5.2 --- Negative gm --- p.55Chapter 3.5.3 --- Phase noise calculation --- p.56Chapter 3.5.4 --- Coupling coefficient --- p.57Chapter 3.5.5 --- Low-voltage and low-power design --- p.59Chapter 3.5.6 --- Layout Consideration --- p.61Chapter 3.5.6.1 --- Symmetrical Layout and parasitics --- p.61Chapter 3.5.6.2 --- Metal width and number of vias --- p.63Chapter 3.5.6.3 --- Substrate contact and guard ring --- p.63Chapter 3.5.7 --- Simulation Results --- p.65Chapter 3.5.7.1 --- Frequency and output power --- p.65Chapter 3.5.7.2 --- Quadrature signal generation --- p.67Chapter 3.5.7.3 --- Tuning range --- p.67Chapter 3.5.7.4 --- Power consumption --- p.68Chapter 3.5.7.5 --- Phase noise --- p.69Chapter 3.6 --- Polyphase filter and Single-sideband mixer design --- p.70Chapter 3.6.1 --- Polyphase filter --- p.72Chapter 3.6.2 --- Layout Consideration --- p.74Chapter 3.6.3 --- Simulation results --- p.76Chapter 3.7 --- Comparison with parallel-coupled QVCO --- p.78Chapter CHAPTER 4 --- EXPERIMENTAL RESULTS --- p.80Chapter 4.1 --- Test Fixture --- p.82Chapter 4.2 --- Measurement set-up --- p.84Chapter 4.3 --- Measurement results --- p.86Chapter 4.3.1 --- Proposed QVCO using back-gate superharmonic coupling --- p.86Chapter 4.3.1.1 --- Output Spectrum --- p.86Chapter 4.3.1.2 --- Tuning range --- p.87Chapter 4.3.1.3 --- Phase noise --- p.88Chapter 4.3.1.4 --- Power consumption --- p.88Chapter 4.3.1.5 --- Image-rejection ratio --- p.89Chapter 4.3.2 --- Parallel-coupled QVCO --- p.90Chapter 4.3.2.1 --- Output spectrum --- p.90Chapter 4.3.2.2 --- Power consumption --- p.90Chapter 4.3.2.3 --- Tuning range --- p.91Chapter 4.3.2.4 --- Phase noise --- p.92Chapter 4.3.3 --- Comparison between proposed and parallel-coupled QVCO --- p.93Chapter CHAPTER 5 --- CONCLUSIONS --- p.95Chapter 5.1 --- Conclusions --- p.95Chapter 5.2 --- Future work --- p.97REFERENCES --- p.9

    An Integrated Subharmonic Coupled-Oscillator Scheme for a 60-GHz Phased-Array Transmitter

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    This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 × 2 array demonstrates a 200–MHz locking range and 1 × 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below 100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors’ knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process

    Low-power transceiver design for mobile wireless chemical biological sensors

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    The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to Ad hoc network architecture remains a challenge. This work involves the design of a Transceiver for a mobile chemical sensor. The transceiver design integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, a Voltage Controlled Oscillator with injection locking, Gilbert cell mixers, and a Class E Power amplifier making it as a single-chip transceiver. This proposed low power 2GHz transceiver has been designed in TSMC 0.35~lm CMOS process using Cadence electronic design automation tools. Post layout HSPICE simulation indicates that Design meets the separation of noise levels by 52dB and 42dB in transmitter and receiver respectively with power consumption of 56 mW and 38 mW in transmit and receive mode

    Superharmonic Injection Locked Quadrature LC VCO Using Current Recycling Architecture

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    Quadrature LO signal is a key element in many of the RF transceivers which tend to dominate today’s wireless communication technology. The design of a quadrature LC VCO with better phase noise and lower power consumption forms the core of this work. This thesis investigates a coupling mechanism to implement a quadrature voltage controlled oscillator using indirect injection method. The coupling network in this QVCO couples the two LC cores with their super-harmonic and it recycles its bias current back into the LC tank such that the power consumed by the coupling network is insignificant. This recycled current enables the oscillator to achieve higher amplitude of oscillation for the same power consumption compared to conventional design, hence assuring better phase noise. Mathematical analysis has been done to study the mechanism of quadrature operation and mismatch effects of devices on the quadrature phase error of the proposed QVCO. The proposed quadrature LC VCO is designed in TSMC 0.18 μm technology. It is tunable from 2.61 GHz - 2.85 GHz with sensitivity of 240 MHz/V. Its worst case phase noise is -120 dBc/Hz at 1 MHz offset. The total layout area is 1.41 mm^2 and the QVCO core totally draws 3 mA current from 1.8 V supply

    The Effect of DC Component on CMOS Injection-Coupled LC Quadrature Oscillator (IC-QO)

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    This paper creates a different insight to improve phase noise of Injection-Coupled quadrature oscillators (QOs). In fact, there are several phase noise functions and the important parameter is carrier power that considered here. The QO is analyzed and the mismatches between LC tanks that are the main proofs of phase error in this oscillator are shown. The main aim of this paper is focused on the reduction of phase noise by considering DC term. It is shown that the DC level which ignored in the most previous works is also important to improve phase noise by the carrier power. With due attention in the previous equations the phase noise can be reduced and the phase error can be cancelled or controlled by adjusting bias current. On the other hand as a result, is obtained that increasing of the drain current and the voltage of LC tank decrease the phase noise and the phase error simultaneously. To confirm the proposed idea and analysis, a 5.5 GHz QO is designed and simulated using 0.18µm TSMC CMOS technology. The simulation results show confirmation of the proposed idea

    A Q-band Direct Divide-by-4 Injection-Locked Frequency Divider with Quadrature Outputs

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    [[abstract]]A divide-by-4 injection-locked frequency divider is designed for applications in the millimeter-wave frequency range. The proposed circuit also features in quadrature phase outputs by using a quadrature voltage-controlled oscillator. The input signal is injected into the common-mode node at the tail current source directly. Implemented in a 0.13 μm CMOS technology, the core circuit consumes dc power of 3.66mW with 1.2 V supply voltage. The operation range achieves 1.95 GHz. The entire die occupies an area of 974Ã726 um 2 .[[conferencetype]]國際[[conferencedate]]20100928~2010093

    A Wideband Quadrature VCO Using a Novel Tail Current-Clipping Technique

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    This thesis presents a Quadrature VCO (QVCO) architecture using a novel tail current-clipping technique that improves the phase noise performance of a traditional QVCO by about 4 dB while obtaining a tuning range of about 4 to 5 GHz. This work introduces an innovative idea based on a new approach of implementing a QVCO without an explicit conventional parallel or series coupling network and eliminates some of the issues associated with a traditional QVCO such as bimodal oscillations and phase noise degradation due to the coupling network. The proposed structure has a lot of advantages over the traditional P-QVCO in terms of both phase noise and power consumption. The proposed QVCO was fabricated in the 40 nm CMOS technology. The measured phase noise at 4.9 GHz was about -123.2 dBc/Hz at 1 MHz offset frequency while the quadrature error was less than 3° over the complete tuning range. The proposed architecture consumes a power of about 7.5 mW from a supply of 1.1 V with a figure-of-merit (FoM) of 188.27 dBc/Hz at 4.9 GHz output frequency

    A Wideband Injection-Locking Scheme and Quadrature Phase Generation in 65-nm CMOS

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    A novel technique for wideband injection locking in an LC oscillator is proposed. Phased-lock-loop and injection-locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter. This method does not require a phase frequency detector or a loop filter to achieve phase lock. A mathematical analysis of the system is presented and the expression for new locking range is derived. A locking range of 13.4-17.2 GHz and an average jitter tracking bandwidth of up to 400 MHz were measured in a high- Q LC oscillator. This architecture is used to generate quadrature phases from a single clock without any frequency division. It also provides high-frequency jitter filtering while retaining the low-frequency correlated jitter essential for forwarded clock receivers
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